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* [rpms/intel-lpmd] f43: Bump to git mainline
@ 2026-09-11 2:58 Neal Gompa
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From: Neal Gompa @ 2026-09-11 2:58 UTC (permalink / raw)
To: git-commits
A new commit has been pushed.
Repo : rpms/intel-lpmd
Branch : f43
Commit : 6bd4eab1f7762849a38eaf1dde0d88186219fb44
Author : Neal Gompa <ngompa@fedoraproject.org>
Date : 2026-09-10T22:54:53-04:00
Stats : +601/-3 in 4 file(s)
URL : https://src.fedoraproject.org/rpms/intel-lpmd/c/6bd4eab1f7762849a38eaf1dde0d88186219fb44?branch=f43
Log:
Bump to git mainline
- Add patches for Arrow Lake-H and Wildcat Lake support (rhbz#2531738)
---
diff --git a/0101-config-arrowlake-h-enabling.patch b/0101-config-arrowlake-h-enabling.patch
new file mode 100644
index 0000000..1e0e966
--- /dev/null
+++ b/0101-config-arrowlake-h-enabling.patch
@@ -0,0 +1,294 @@
+From ed3438a4fa41421c2262ac51ff3f26f485c945da Mon Sep 17 00:00:00 2001
+From: Joy Philip Pilli <joyphilip.p2001@gmail.com>
+Date: Sun, 21 Jun 2026 06:19:59 +0530
+Subject: [PATCH] config: arrowlake-h enabling
+
+Signed-off-by: Joy Philip Pilli <joyphilip.p2001@gmail.com>
+---
+ data/Makefile.am | 1 +
+ data/intel_lpmd_config_F6_M197.xml | 244 +++++++++++++++++++++++++++++
+ src/lpmd_cpu.c | 3 +-
+ 3 files changed, 247 insertions(+), 1 deletion(-)
+ create mode 100644 data/intel_lpmd_config_F6_M197.xml
+
+diff --git a/data/Makefile.am b/data/Makefile.am
+index a67bfde..b9a1366 100644
+--- a/data/Makefile.am
++++ b/data/Makefile.am
+@@ -32,6 +32,7 @@ lpmd_config_DATA = \
+ intel_lpmd_config_F6_M170.xml \
+ intel_lpmd_config_F6_M181.xml \
+ intel_lpmd_config_F6_M189.xml \
++ intel_lpmd_config_F6_M197.xml \
+ intel_lpmd_config_F6_M204.xml
+
+ EXTRA_DIST = \
+diff --git a/data/intel_lpmd_config_F6_M197.xml b/data/intel_lpmd_config_F6_M197.xml
+new file mode 100644
+index 0000000..5dd5f35
+--- /dev/null
++++ b/data/intel_lpmd_config_F6_M197.xml
+@@ -0,0 +1,244 @@
++<?xml version="1.0"?>
++
++<!--
++Intel Energy Optimizer (LPMD) configuration for Arrow Lake-H
++(family 6, model 0xC5 / 197).
++
++ Performance (PerformanceDef=-1) -> LPMD_OFF -> all CPUs active
++ Balanced (BalancedDef= 0) -> LPMD_AUTO -> E+L cores only (P-cores parked)
++ Powersaver (PowersaverDef= 1) -> LPMD_ON -> L-cores only
++
++Design: P-cores are NEVER used in Balanced mode. All WLT states use
++ActiveLcores=ALL + ActiveEcores=ALL (topology-portable, not hardcoded
++CPU numbers). EPP/EPB vary per WLT state to spread the power-performance
++tradeoff across E+L cores. If the user wants P-cores, they select
++Performance mode or disable LPMD.
++-->
++
++<Configuration>
++ <!--
++ CPU format example: 1,2,4..6,8-10
++ Used by the force-on path (PowersaverDef=1).
++ -->
++ <lp_mode_cpus></lp_mode_cpus>
++
++ <!--
++ EPP to use in Low Power Mode
++ 0-255: Valid EPP value to use in Low Power Mode
++ -1: Don't change EPP in Low Power Mode
++ Left empty: LPMD does not override EPP — it stays under
++ PPD (power-profiles-daemon) control.
++ -->
++ <lp_mode_epp></lp_mode_epp>
++
++ <!--
++ Mode values
++ 0: Cgroup v2
++ 1: Cgroup v2 isolate
++ 2: CPU idle injection
++ -->
++ <Mode>1</Mode>
++
++ <!--
++ Default behavior when Performance power setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <PerformanceDef>-1</PerformanceDef>
++
++ <!--
++ Default behavior when Balanced power setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <BalancedDef>0</BalancedDef>
++
++ <!--
++ Default behavior when Power saver setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <PowersaverDef>1</PowersaverDef>
++
++ <!--
++ Use HFI LPM hints
++ 0 : No
++ 1 : Yes
++ -->
++ <HfiLpmEnable>0</HfiLpmEnable>
++
++ <!--
++ Use WLT hints
++ 0 : No
++ 1 : Yes
++ -->
++ <WLTHintEnable>1</WLTHintEnable>
++
++ <!--
++ Use WLT hint Poll enable
++ 0 : No
++ 1 : Yes
++ -->
++ <WLTHintPollEnable>1</WLTHintPollEnable>
++
++ <!--
++ Use HFI SUV hints
++ 0 : No
++ 1 : Yes
++ NOTE: SUV mode support was removed from the daemon (May 2025).
++ The parser accepts this element but discards the value.
++ Kept here for forward compatibility if the feature is restored.
++ -->
++ <HfiSuvEnable>0</HfiSuvEnable>
++
++ <!--
++ WLT hint mask: ANDed with the raw hardware WLT hint before
++ matching against each state's WLTType.
++ 15 (0x0F) keeps the low 4 bits, which covers the defined
++ WLT classifications (0=Idle, 1=Battery Life, 2=Sustained, 3=Bursty).
++ Arrow Lake currently only produces values 0-3, so mask=15
++ is a no-op today — it serves as a forward-compatibility guard
++ in case future firmware uses upper bits for extended flags.
++ Set to -1 to disable masking entirely.
++ -->
++ <WLTHintMask>15</WLTHintMask>
++
++ <!--
++ Global utilization thresholds (0-100). Used by the legacy
++ UTIL_POWER fallback path when no per-state <States> config
++ exists. Since this config defines <States>, these globals
++ are not consumed — but kept for documentation and in case
++ the <States> block is removed.
++
++ util_entry_threshold: max system-wide load (%) to enter LPM.
++ util_exit_threshold: max busiest-CPU load (%) to stay in LPM
++ (despite the name, it gates entry matching, not exit).
++ Clearing both disables the util monitor entirely.
++
++ Disabled here: in AUTO mode, all states resolve to E+L cores
++ (P-cores always parked), so load-based exit is unnecessary —
++ the CPU mask never changes, only EPP/EPB varies by WLT state.
++
++ <util_entry_threshold>10</util_entry_threshold>
++ <util_exit_threshold>95</util_exit_threshold>
++ -->
++
++ <!--
++ EntryDelayMS / ExitDelayMS / EntryHystMS / ExitHystMS are
++ currently parsed but have no runtime effect. Omitted here.
++ -->
++
++ <!--
++ Ignore ITMT setting during LP-mode enter/exit
++ 0: disable ITMT upon LP-mode enter and re-enable ITMT upon LP-mode exit
++ 1: do not touch ITMT setting during LP-mode enter/exit
++
++ Arrow Lake-H supports Turbo Boost Max Technology 3.0, but ITMT
++ is effectively a no-op here for two reasons:
++ 1. lpmd parks P-cores via cgroup isolation — ITMT tells the
++ scheduler to *prefer* P-cores, the opposite of what LPM does.
++ 2. On kernel 6.14+, the toggle moved from sysctl to debugfs and
++ is only created when a driver (intel_pstate / HFI) registers
++ ITMT priorities. On kernel 6.17 with Arrow Lake-H, the toggle
++ file is not created, so the daemon logs ERR and continues.
++ Kept at 0 for consistency with upstream configs (F6_M170/189/204).
++ -->
++ <IgnoreITMT>0</IgnoreITMT>
++
++ <!--
++ SoC Power Slider (BalancedSliderAC/DC, SliderOffsetAC/DC): omitted.
++ The slider is a Panther Lake hardware debut — Arrow Lake does not
++ expose the slider mailbox via the int340x thermal driver, so the
++ processor_thermal_soc_slider module loads but does not register a
++ platform-profile device. See F6_M204 config for Panther Lake values.
++ -->
++
++ <!--
++ WorkLoad Type hint states for Arrow Lake-H.
++
++ P-cores are NEVER activated in Balanced/AUTO mode. All states
++ use ActiveLcores=ALL + ActiveEcores=ALL (resolved at runtime to
++ the actual E+L CPU set) so the mask is topology-portable and
++ not hardcoded to specific CPU numbers.
++
++ EPP/EPB are differentiated per WLT state so E-cores and L-cores
++ operate on a power-performance spectrum under Speed Shift /
++ Thread Director control:
++
++ UTIL_IDLE (WLT 0+1): EPP=192 "balance_power", EPB=8
++ Idle or unclassified workload. Power-biased but E-cores
++ can still respond to light interactive tasks.
++
++ UTIL_IDLE_SUSTAIN (WLT 2): EPP=64, EPB=4
++ Sustained compute. Lets E-cores boost for real work while
++ P-cores stay parked.
++
++ UTIL_IDLE_BURSTY (WLT 3): EPP=128 "balance_performance", EPB=6
++ Bursty spikes. Moderate — E-cores absorb bursts without
++ sustaining high power draw.
++
++ WLTTypeMask=3 on UTIL_IDLE merges WLT=0 (WLT_IDLE / deep idle)
++ and WLT=1 (WLT_BATTERY_LIFE / light usage) into one state.
++
++ WARNING: Do NOT split WLT 0 and 1 into separate states with
++ different EPP/EPB values. The hardware oscillates
++ rapidly between WLT=0 and WLT=1 (~2x/sec observed in logs), and
++ since the EPP/EPB values would genuinely differ between the
++ two states, a value-change guard (like cgroup's "skip if
++ cpumask unchanged") cannot suppress the sysfs writes — each
++ transition would produce ~cpu-cores-count x 2 real writes
++ (ex. 16 CPUs x EPP+EPB = ~32 sysfs writes). The power cost
++ of that I/O churn outweighs any benefit from a more aggressive
++ EPP during brief WLT=0 moments. If deep idle power savings
++ are needed, Power Saver mode (L-cores only, EPP=255) already
++ provides that.
++
++ Note on invalid/unexpected WLT values: some platform configs
++ (e.g. F6_M189) use a wildcard state with no WLTType to
++ catch all unmatched WLT values including invalid ones. Here,
++ WLTTypeMask=3 provides targeted handling — WLT 0 and 1 are
++ explicitly matched to UTIL_IDLE, while invalid or out-of-
++ range values (e.g. WLT_INVALID=4 from sysfs read failures)
++ match no state and the daemon holds its current state
++ unchanged (STATE_NONE in choose_next_state).
++ -->
++ <States>
++ <CPUFamily> 6 </CPUFamily>
++ <CPUModel> 197 </CPUModel>
++ <CPUConfig> * </CPUConfig>
++ <State>
++ <ID> 1 </ID>
++ <Name> UTIL_IDLE </Name>
++ <WLTTypeMask> 3 </WLTTypeMask>
++ <ActiveLcores>ALL</ActiveLcores>
++ <ActiveEcores>ALL</ActiveEcores>
++ <IRQMigrate>1</IRQMigrate>
++ <EPP>192</EPP>
++ <EPB>8</EPB>
++ </State>
++ <State>
++ <ID> 2 </ID>
++ <Name> UTIL_IDLE_SUSTAIN </Name>
++ <WLTType> 2 </WLTType>
++ <ActiveLcores>ALL</ActiveLcores>
++ <ActiveEcores>ALL</ActiveEcores>
++ <IRQMigrate>1</IRQMigrate>
++ <EPP>64</EPP>
++ <EPB>4</EPB>
++ </State>
++ <State>
++ <ID> 3 </ID>
++ <Name> UTIL_IDLE_BURSTY </Name>
++ <WLTType> 3 </WLTType>
++ <ActiveLcores>ALL</ActiveLcores>
++ <ActiveEcores>ALL</ActiveEcores>
++ <IRQMigrate>1</IRQMigrate>
++ <EPP>128</EPP>
++ <EPB>6</EPB>
++ </State>
++ </States>
++
++</Configuration>
+diff --git a/src/lpmd_cpu.c b/src/lpmd_cpu.c
+index f4c9cbd..04ec4d1 100644
+--- a/src/lpmd_cpu.c
++++ b/src/lpmd_cpu.c
+@@ -23,9 +23,10 @@ static struct cpu_model_entry id_table[] = {
+ { 6, 0xbf }, // Raptorlake S
+ { 6, 0xaa }, // Meteorlake
+ { 6, 0xac }, // Meteorlake
+- { 6, 0xb5 }, // ArrowLake
++ { 6, 0xb5 }, // Arrowlake U
+ { 6, 0xbd }, // Lunarlake
+ { 6, 0xcc }, // Pantherlake
++ { 6, 0xc5 }, // Arrowlake H
+ { 0, 0 } // Last Invalid entry
+ };
+
+--
+2.55.0
+
diff --git a/0102-config-enable-Wildcat-Lake-in-LPMD.patch b/0102-config-enable-Wildcat-Lake-in-LPMD.patch
new file mode 100644
index 0000000..09ae44f
--- /dev/null
+++ b/0102-config-enable-Wildcat-Lake-in-LPMD.patch
@@ -0,0 +1,293 @@
+From 979044a3ce87bd753062e08c62466e2a5599b36b Mon Sep 17 00:00:00 2001
+From: Karan Shukla <karan_shukla@live.com>
+Date: Tue, 28 Jul 2026 07:26:12 -0400
+Subject: [PATCH] config: enable Wildcat Lake in LPMD
+
+---
+ data/Makefile.am | 3 +-
+ data/intel_lpmd_config_F6_M213.xml | 246 +++++++++++++++++++++++++++++
+ src/lpmd_cpu.c | 1 +
+ 3 files changed, 249 insertions(+), 1 deletion(-)
+ create mode 100644 data/intel_lpmd_config_F6_M213.xml
+
+diff --git a/data/Makefile.am b/data/Makefile.am
+index b9a1366..1ac0910 100644
+--- a/data/Makefile.am
++++ b/data/Makefile.am
+@@ -33,7 +33,8 @@ lpmd_config_DATA = \
+ intel_lpmd_config_F6_M181.xml \
+ intel_lpmd_config_F6_M189.xml \
+ intel_lpmd_config_F6_M197.xml \
+- intel_lpmd_config_F6_M204.xml
++ intel_lpmd_config_F6_M204.xml \
++ intel_lpmd_config_F6_M213.xml
+
+ EXTRA_DIST = \
+ intel_lpmd.service.in \
+diff --git a/data/intel_lpmd_config_F6_M213.xml b/data/intel_lpmd_config_F6_M213.xml
+new file mode 100644
+index 0000000..ef39aa0
+--- /dev/null
++++ b/data/intel_lpmd_config_F6_M213.xml
+@@ -0,0 +1,246 @@
++<?xml version="1.0"?>
++
++<!--
++Intel Energy Optimizer (LPMD) configuration for Wildcat Lake
++(family 6, model 0xD5 / 213).
++
++ Performance (PerformanceDef=-1) -> LPMD_OFF -> all CPUs active (P+L)
++ Balanced (BalancedDef= 0) -> LPMD_AUTO -> L-cores only (P-cores parked)
++ Powersaver (PowersaverDef= 1) -> LPMD_ON -> L-cores only (forced)
++
++Design: verified on an Intel Core 5 320 (2 P-cores, 15W TDP) via the
++daemon's own CPUID-based core-type detection (lpmd_cpu.c:detect_cpu_topo,
++which classifies atom-type cores as E vs L by whether their CPUID leaf 4
++reports an L3 slice): "Detected 2 Pcores, 0 Ecores, 4 Lcores, TDP 15W".
++All 4 non-P cores land in the L tier, not E — there is no full E-core
++tier on this sample, only P + L. This does NOT match what /sys/devices
++alone would suggest: /sys/devices/cpu_core/cpus (0-1) and
++/sys/devices/cpu_atom/cpus (2-5) only distinguish big/little, not the
++E-vs-L split the daemon's own cache-topology probe makes, and lscpu -e's
++L2-instance grouping (cores 2-5 sharing one L2 cluster) looks superficially
++like a single Skymont-style E-core module. Trust the daemon's own
++detect_cpu_topo() output over either of those when writing a config for
++this model — an earlier draft of this file used ActiveEcores=ALL, which
++would have resolved to an empty CPU set at runtime and left Balanced/
++Powersaver mode with zero active cores.
++
++Only the idle states park the P-cores. UTIL_IDLE uses ActiveLcores=ALL
++(topology-portable, not hardcoded CPU numbers); UTIL_IDLE_SUSTAIN and
++UTIL_IDLE_BURSTY release the full CPU set, following F6_M181 and F6_M204.
++EPP/EPB additionally vary per WLT state.
++-->
++
++<Configuration>
++ <!--
++ CPU format example: 1,2,4..6,8-10
++ Used by the force-on path (PowersaverDef=1).
++ -->
++ <lp_mode_cpus></lp_mode_cpus>
++
++ <!--
++ EPP to use in Low Power Mode
++ 0-255: Valid EPP value to use in Low Power Mode
++ -1: Don't change EPP in Low Power Mode
++ Left empty: LPMD does not override EPP — it stays under
++ PPD (power-profiles-daemon) control.
++ -->
++ <lp_mode_epp></lp_mode_epp>
++
++ <!--
++ Mode values
++ 0: Cgroup v2
++ 1: Cgroup v2 isolate
++ 2: CPU idle injection
++ -->
++ <Mode>1</Mode>
++
++ <!--
++ Default behavior when Performance power setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <PerformanceDef>-1</PerformanceDef>
++
++ <!--
++ Default behavior when Balanced power setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <BalancedDef>0</BalancedDef>
++
++ <!--
++ Default behavior when Power saver setting is used
++ -1: force off. (Never enter Low Power Mode)
++ 1: force on. (Always stay in Low Power Mode)
++ 0: auto. (opportunistic Low Power Mode enter/exit)
++ -->
++ <PowersaverDef>1</PowersaverDef>
++
++ <!--
++ Use HFI LPM hints
++ 0 : No
++ 1 : Yes
++ -->
++ <HfiLpmEnable>0</HfiLpmEnable>
++
++ <!--
++ Use WLT hints
++ 0 : No
++ 1 : Yes
++ -->
++ <WLTHintEnable>1</WLTHintEnable>
++
++ <!--
++ Use WLT hint Poll enable
++ 0 : No
++ 1 : Yes
++ -->
++ <WLTHintPollEnable>1</WLTHintPollEnable>
++
++ <!--
++ Use HFI SUV hints
++ 0 : No
++ 1 : Yes
++ NOTE: SUV mode support was removed from the daemon (May 2025).
++ The parser accepts this element but discards the value.
++ Kept here for forward compatibility if the feature is restored.
++ -->
++ <HfiSuvEnable>0</HfiSuvEnable>
++
++ <!--
++ WLT hint mask: ANDed with the raw hardware WLT hint before
++ matching against each state's WLTType.
++ 15 (0x0F) keeps the low 4 bits, which covers the defined
++ WLT classifications (0=Idle, 1=Battery Life, 2=Sustained, 3=Bursty).
++ -->
++ <WLTHintMask>15</WLTHintMask>
++
++ <!--
++ Global utilization thresholds (0-100). Used by the legacy
++ UTIL_POWER fallback path when no per-state <States> config
++ exists. Since this config defines <States>, these globals
++ are not consumed — kept for documentation only.
++
++ Disabled here regardless: every state below defines a WLTType
++ or WLTTypeMask, and per intel_lpmd_config.xml(5) a state with
++ WLTType defined does not use utilization-based entry triggers.
++ LPM entry and exit are driven entirely by the WLT hint.
++
++ <util_entry_threshold>10</util_entry_threshold>
++ <util_exit_threshold>95</util_exit_threshold>
++ -->
++
++ <!--
++ EntryDelayMS / ExitDelayMS / EntryHystMS / ExitHystMS are
++ currently parsed but have no runtime effect. Omitted here.
++ -->
++
++ <!--
++ Ignore ITMT setting during LP-mode enter/exit
++ 0: disable ITMT upon LP-mode enter and re-enable ITMT upon LP-mode exit
++ 1: do not touch ITMT setting during LP-mode enter/exit
++
++ lpmd parks P-cores via cgroup isolation; ITMT tells the scheduler
++ to *prefer* P-cores, the opposite of what LPM does here. Kept at
++ 0 for consistency with upstream configs (F6_M170/189/204/197).
++ -->
++ <IgnoreITMT>0</IgnoreITMT>
++
++ <!--
++ SoC Power Slider (BalancedSliderAC/DC, SliderOffsetAC/DC): omitted.
++ Not yet confirmed present on Wildcat Lake via the int340x thermal
++ driver on this sample; can be added once verified on hardware that
++ exposes the slider mailbox. See F6_M204 (Panther Lake) for the
++ values to model if/when confirmed.
++ -->
++
++ <!--
++ WorkLoad Type hint states for Wildcat Lake.
++
++ The P-cores are parked only in the idle states. This platform's
++ lower tier is the L-core set (see topology note above:
++ detect_cpu_topo() classifies all 4 non-P cores as L, not E), and
++ UTIL_IDLE uses ActiveLcores=ALL, resolved at runtime to the actual
++ L-core mask, so it is topology-portable rather than hardcoded to
++ specific CPU numbers.
++
++ UTIL_IDLE_SUSTAIN and UTIL_IDLE_BURSTY release the full CPU set
++ via ActiveCPUs=*, matching F6_M181 (Lunar Lake) and F6_M204
++ (Panther Lake). Every upstream config that varies the CPU set by
++ WLT state unparks for both 2 and 3; none unparks for one alone.
++ Per the DPTF definitions, WLT 3 has real idle periods between
++ bursts, so finishing a burst on the P-cores returns the SoC to
++ idle sooner, and WLT 2 is by definition already exhausting RAPL
++ PL1/PL2, so the extra cores complete the work inside a power
++ budget that is capped either way.
++
++ An earlier revision of this file parked the P-cores in all three
++ states. The daemon behaved correctly — the WLT hint moves to 2
++ within ~1s of sustained load and UTIL_IDLE_SUSTAIN is entered,
++ observed via EPP 192->64 and EPB 8->4 — but every state it could
++ reach also excluded the P-cores, so cpuset.cpus.isolated never
++ cleared. Adding EntrySystemLoadThres does not fix that: per
++ intel_lpmd_config.xml(5), "if [WLTType] is defined then
++ utilization based entry triggers are not used".
++
++ EPP/EPB are differentiated per WLT state:
++
++ UTIL_IDLE (WLT 0+1): EPP=192 "balance_power", EPB=8
++ Idle or light activity. Power-biased, P-cores parked, but
++ the L-cores can still respond to light interactive tasks.
++
++ UTIL_IDLE_SUSTAIN (WLT 2): EPP=64, EPB=4
++ Sustained compute. Full CPU set, performance-biased.
++
++ UTIL_IDLE_BURSTY (WLT 3): EPP=128 "balance_performance", EPB=6
++ Bursty spikes. Full CPU set so bursts retire quickly, but
++ biased more toward power than the sustained state.
++
++ EPP/EPB values for states 2 and 3 are taken from F6_M181, whose
++ WLTTypeMask=3 idle state this config otherwise mirrors.
++
++ WLTTypeMask=3 on UTIL_IDLE merges WLT=0 (WLT_IDLE / deep idle)
++ and WLT=1 (WLT_BATTERY_LIFE / light usage) into one state, since
++ the hardware oscillates between the two rapidly (~2x/sec
++ observed on other hybrid platforms in this family) and splitting
++ them would cause needless sysfs write churn for no real EPP/EPB
++ benefit. See F6_M197 (Arrow Lake-H) for the full rationale.
++
++ Invalid/out-of-range WLT values (e.g. WLT_INVALID=4) match no
++ state; the daemon holds its current state unchanged rather than
++ falling back to a wildcard.
++ -->
++ <States>
++ <CPUFamily> 6 </CPUFamily>
++ <CPUModel> 213 </CPUModel>
++ <CPUConfig> * </CPUConfig>
++ <State>
++ <ID> 1 </ID>
++ <Name> UTIL_IDLE </Name>
++ <WLTTypeMask> 3 </WLTTypeMask>
++ <ActiveLcores>ALL</ActiveLcores>
++ <IRQMigrate>1</IRQMigrate>
++ <EPP>192</EPP>
++ <EPB>8</EPB>
++ </State>
++ <State>
++ <ID> 2 </ID>
++ <Name> UTIL_IDLE_SUSTAIN </Name>
++ <WLTType> 2 </WLTType>
++ <ActiveCPUs> * </ActiveCPUs>
++ <EPP>64</EPP>
++ <EPB>4</EPB>
++ </State>
++ <State>
++ <ID> 3 </ID>
++ <Name> UTIL_IDLE_BURSTY </Name>
++ <WLTType> 3 </WLTType>
++ <ActiveCPUs> * </ActiveCPUs>
++ <EPP>128</EPP>
++ <EPB>6</EPB>
++ </State>
++ </States>
++
++</Configuration>
+diff --git a/src/lpmd_cpu.c b/src/lpmd_cpu.c
+index 04ec4d1..1d8ce60 100644
+--- a/src/lpmd_cpu.c
++++ b/src/lpmd_cpu.c
+@@ -27,6 +27,7 @@ static struct cpu_model_entry id_table[] = {
+ { 6, 0xbd }, // Lunarlake
+ { 6, 0xcc }, // Pantherlake
+ { 6, 0xc5 }, // Arrowlake H
++ { 6, 0xd5 }, // Wildcatlake
+ { 0, 0 } // Last Invalid entry
+ };
+
+--
+2.55.0
+
diff --git a/intel-lpmd.spec b/intel-lpmd.spec
index 17966f3..987e71a 100644
--- a/intel-lpmd.spec
+++ b/intel-lpmd.spec
@@ -1,13 +1,24 @@
%global daemon_name intel_lpmd
+%global commit 40d18a6cc22c37addc3e636bc9c5cf1ab5d5fbda
+%global commitdate 20260608
+%global shortcommit %{sub %{commit} 1 7}
+
Name: intel-lpmd
-Version: 0.1.0
+Version: 0.1.0^git%{commitdate}.%{shortcommit}
Release: %autorelease
Summary: Intel Low Power Mode Daemon
License: GPL-2.0-or-later
URL: https://github.com/intel/intel-lpmd
-Source: %{url}/archive/v%{version}/%{name}-%{version}.tar.gz
+%dnl Source: %{url}/archive/v%{version}/%{name}-%{version}.tar.gz
+Source: %{url}/archive/%{commit}/%{name}-%{shortcommit}.tar.gz
+
+# Proposed upstream
+## Arrow Lake H support: https://github.com/intel/intel-lpmd/pull/121
+Patch0101: 0101-config-arrowlake-h-enabling.patch
+## Wildcat Lake support: https://github.com/intel/intel-lpmd/pull/124
+Patch0102: 0102-config-enable-Wildcat-Lake-in-LPMD.patch
ExclusiveArch: %{x86_64}
diff --git a/sources b/sources
index f78d4a7..2b3ec6b 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-SHA512 (intel-lpmd-0.1.0.tar.gz) = 45f18b7c98814af6f56659fcf63d32cfb3df3daa93bb6561b271094d5a2d91d50589a50475ae3b59aaeaca489e76a45879754a74af0dad443686697269f8b51d
+SHA512 (intel-lpmd-40d18a6.tar.gz) = 3f18a27ac5a70a6240c02b8b9157846071167e1e9aee5db06cd2755c378382f869ce2594d409092534f924cdc0ea7ae0ebed14b85cc5f25bb68cac8b67efb92c
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