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* [rpms/gcc] rhel-f41-base: 10.0.1-0.11
@ 2026-06-29 12:28 Jakub Jelinek
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From: Jakub Jelinek @ 2026-06-29 12:28 UTC (permalink / raw)
To: git-commits
A new commit has been pushed.
Repo : rpms/gcc
Branch : rhel-f41-base
Commit : 643c97a3d8490ca6940a63a7d6cf1395e806e4d9
Author : Jakub Jelinek <jakub@redhat.com>
Date : 2020-03-28T11:00:41+01:00
Stats : +172/-84 in 7 file(s)
URL : https://src.fedoraproject.org/rpms/gcc/c/643c97a3d8490ca6940a63a7d6cf1395e806e4d9?branch=rhel-f41-base
Log:
10.0.1-0.11
---
diff --git a/.gitignore b/.gitignore
index b3422f4..a320272 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,3 +8,4 @@
/gcc-10.0.1-20200216.tar.xz
/gcc-10.0.1-20200311.tar.xz
/gcc-10.0.1-20200325.tar.xz
+/gcc-10.0.1-20200328.tar.xz
diff --git a/gcc.spec b/gcc.spec
index 34f3a13..131b321 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -1,10 +1,10 @@
-%global DATE 20200325
-%global gitrev 17146084e899406b7b39093e945561c737dfe02c
+%global DATE 20200328
+%global gitrev 97ad35f30b0d8ed5376febf09cefa2b93f9dc423
%global gcc_version 10.0.1
%global gcc_major 10
# Note, gcc_release must be integer, if you want to add suffixes to
# %%{release}, append them after %%{gcc_release} on Release: line.
-%global gcc_release 0.10
+%global gcc_release 0.11
%global nvptx_tools_gitrev 5f6f343a302d620b0868edab376c00b15741e39e
%global newlib_cygwin_gitrev 50e2a63b04bdd018484605fbb954fd1bd5147fa0
%global _unpackaged_files_terminate_build 0
@@ -180,6 +180,7 @@ BuildRequires: gdb
BuildRequires: glibc-devel >= 2.4.90-13
BuildRequires: elfutils-devel >= 0.147
BuildRequires: elfutils-libelf-devel >= 0.147
+BuildRequires: libzstd-devel
%ifarch ppc ppc64 ppc64le ppc64p7 s390 s390x sparc sparcv9 alpha
# Make sure glibc supports TFmode long double
BuildRequires: glibc >= 2.3.90-35
@@ -264,8 +265,8 @@ Patch8: gcc10-foffload-default.patch
Patch9: gcc10-Wno-format-security.patch
Patch10: gcc10-rh1574936.patch
Patch11: gcc10-d-shared-libphobos.patch
-Patch12: gcc10-pr94308.patch
-Patch13: gcc10-pr94254.patch
+Patch12: gcc10-pr93069.patch
+Patch13: gcc10-pr94343.patch
# On ARM EABI systems, we do want -gnueabi to be part of the
# target triple.
@@ -777,8 +778,8 @@ to NVidia PTX capable devices if available.
%patch10 -p0 -b .rh1574936~
%endif
%patch11 -p0 -b .d-shared-libphobos~
-%patch12 -p0 -b .pr94308~
-%patch13 -p0 -b .pr94254~
+%patch12 -p0 -b .pr93069~
+%patch13 -p0 -b .pr94343~
echo 'Red Hat %{version}-%{gcc_release}' > gcc/DEV-PHASE
@@ -3007,6 +3008,20 @@ end
%endif
%changelog
+* Sat Mar 28 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.11
+- update from trunk
+ - PRs c++/81349, c++/84733, c++/93810, c++/93824, c++/94057, c++/94078,
+ c++/94098, c++/94257, c++/94265, c++/94272, c++/94319, c++/94326,
+ c++/94336, c++/94339, c++/94346, c/93573, debug/94273, debug/94281,
+ debug/94296, debug/94323, fortran/93363, fortran/93957, ipa/94271,
+ lto/94259, middle-end/94004, rtl-optimization/92264, target/94145,
+ target/94220, target/94292, testsuite/94334, tree-optimization/90332,
+ tree-optimization/94131, tree-optimization/94269,
+ tree-optimization/94329, tree-optimization/94352
+- fix x86 vec_extract_{lo,hi}*_mask AVX512* patterns (PR target/93069)
+- fix x86 *one_cmpl*2* AVX512* patterns (PR target/94343)
+- add BuildRequires: libzstd-devel
+
* Wed Mar 25 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.10
- update from trunk
- PRs analyzer/94047, analyzer/94099, analyzer/94105, c++/67960, c++/69694,
diff --git a/gcc10-pr93069.patch b/gcc10-pr93069.patch
new file mode 100644
index 0000000..3451fb6
--- /dev/null
+++ b/gcc10-pr93069.patch
@@ -0,0 +1,70 @@
+2020-03-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/93069
+ * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
+ <store_mask_constraint> instead of m in output operand constraint.
+ (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
+ %{%3%}.
+
+ * gcc.target/i386/avx512vl-pr93069.c: New test.
+ * gcc.dg/vect/pr93069.c: New test.
+
+--- gcc/config/i386/sse.md.jj 2019-12-27 18:16:48.146431083 +0100
++++ gcc/config/i386/sse.md 2019-12-28 14:43:29.181456611 +0100
+@@ -8782,7 +8782,8 @@
+ })
+
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+- [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
++ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
++ "=v,v,<store_mask_constraint>")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:V16FI 1 "<store_mask_predicate>"
+ "v,<store_mask_constraint>,v")
+@@ -8834,7 +8835,8 @@
+ })
+
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
++ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
++ "=v,v,<store_mask_constraint>")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI8F_256 1 "<store_mask_predicate>"
+ "v,<store_mask_constraint>,v")
+@@ -8844,7 +8846,7 @@
+ && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+ if (<mask_applied>)
+- return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
++ return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+ else
+ return "#";
+ }
+--- gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c.jj 2019-12-28 16:31:30.118695074 +0100
++++ gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c 2019-12-28 16:32:16.920990539 +0100
+@@ -0,0 +1,12 @@
++/* PR target/93069 */
++/* { dg-do assemble { target vect_simd_clones } } */
++/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
++/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
++/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
++
++#pragma omp declare simd
++int
++foo (int x, int y)
++{
++ return x == 0 ? x : y;
++}
+--- gcc/testsuite/gcc.dg/vect/pr93069.c.jj 2019-12-28 16:31:01.822121036 +0100
++++ gcc/testsuite/gcc.dg/vect/pr93069.c 2019-12-28 16:30:35.503517205 +0100
+@@ -0,0 +1,10 @@
++/* PR target/93069 */
++/* { dg-do assemble { target vect_simd_clones } } */
++/* { dg-options "-O2 -fopenmp-simd" } */
++
++#pragma omp declare simd
++int
++foo (int x, int y)
++{
++ return x == 0 ? x : y;
++}
diff --git a/gcc10-pr94254.patch b/gcc10-pr94254.patch
deleted file mode 100644
index 408b90a..0000000
--- a/gcc10-pr94254.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-2020-03-23 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/94254
- * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
- FPRs to change between SDmode and DDmode.
-
---- gcc/config/rs6000/rs6000.c
-+++ gcc/config/rs6000/rs6000.c
-@@ -12307,6 +12307,15 @@ rs6000_can_change_mode_class (machine_mode from,
- if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
- return false;
-
-+ /* Allow SD<->DD changes, since SDmode values are stored in
-+ the low half of the DDmode, just like target-independent
-+ code expects. We need to allow at least SD->DD since
-+ rs6000_secondary_memory_needed_mode asks for that change
-+ to be made for SD reloads. */
-+ if ((to == DDmode && from == SDmode)
-+ || (to == SDmode && from == DDmode))
-+ return true;
-+
- if (from_size < 8 || to_size < 8)
- return false;
-
diff --git a/gcc10-pr94308.patch b/gcc10-pr94308.patch
deleted file mode 100644
index 78eeae4..0000000
--- a/gcc10-pr94308.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-2020-03-25 Jakub Jelinek <jakub@redhat.com>
-
- PR target/94308
- * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
- INSN_CODE (insn) to -1 when changing the pattern.
-
- * gcc.target/i386/pr94308.c: New test.
-
---- gcc/config/i386/i386-features.c.jj 2020-03-17 13:50:52.955933209 +0100
-+++ gcc/config/i386/i386-features.c 2020-03-24 19:19:17.801609289 +0100
-@@ -1792,6 +1792,7 @@ ix86_add_reg_usage_to_vzeroupper (rtx_in
- RTVEC_ELT (vec, j) = gen_rtx_SET (reg, reg);
- }
- XVEC (pattern, 0) = vec;
-+ INSN_CODE (insn) = -1;
- df_insn_rescan (insn);
- }
-
---- gcc/testsuite/gcc.target/i386/pr94308.c.jj 2020-03-24 19:32:51.964436310 +0100
-+++ gcc/testsuite/gcc.target/i386/pr94308.c 2020-03-24 19:32:39.848617482 +0100
-@@ -0,0 +1,31 @@
-+/* PR target/94308 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mfpmath=sse -mavx2 -mfma" } */
-+
-+#include <x86intrin.h>
-+
-+void
-+foo (float *x, const float *y, const float *z, unsigned int w)
-+{
-+ unsigned int a;
-+ const unsigned int b = w / 8;
-+ const float *c = y;
-+ const float *d = z;
-+ __m256 e = _mm256_setzero_ps ();
-+ __m256 f, g;
-+ for (a = 0; a < b; a++)
-+ {
-+ f = _mm256_loadu_ps (c);
-+ g = _mm256_loadu_ps (d);
-+ c += 8;
-+ d += 8;
-+ e = _mm256_fmadd_ps (f, g, e);
-+ }
-+ __attribute__ ((aligned (32))) float h[8];
-+ _mm256_storeu_ps (h, e);
-+ _mm256_zeroupper ();
-+ float i = h[0] + h[1] + h[2] + h[3] + h[4] + h[5] + h[6] + h[7];
-+ for (a = b * 8; a < w; a++)
-+ i += (*c++) * (*d++);
-+ *x = i;
-+}
diff --git a/gcc10-pr94343.patch b/gcc10-pr94343.patch
new file mode 100644
index 0000000..c8515df
--- /dev/null
+++ b/gcc10-pr94343.patch
@@ -0,0 +1,78 @@
+2020-03-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/94343
+ * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
+ !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
+ operand is a register. Don't enable masked variants for V*[QH]Imode.
+
+ * gcc.target/i386/avx512f-pr94343.c: New test.
+ * gcc.target/i386/avx512vl-pr94343.c: New test.
+
+--- gcc/config/i386/sse.md.jj 2020-03-06 11:35:46.284074858 +0100
++++ gcc/config/i386/sse.md 2020-03-26 18:49:39.644131577 +0100
+@@ -12796,14 +12796,29 @@ (define_expand "one_cmpl<mode>2"
+ })
+
+ (define_insn "<mask_codefor>one_cmpl<mode>2<mask_name>"
+- [(set (match_operand:VI 0 "register_operand" "=v")
+- (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm")
+- (match_operand:VI 2 "vector_all_ones_operand" "BC")))]
+- "TARGET_AVX512F"
+- "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}"
++ [(set (match_operand:VI 0 "register_operand" "=v,v")
++ (xor:VI (match_operand:VI 1 "nonimmediate_operand" "v,m")
++ (match_operand:VI 2 "vector_all_ones_operand" "BC,BC")))]
++ "TARGET_AVX512F
++ && (!<mask_applied>
++ || <ssescalarmode>mode == SImode
++ || <ssescalarmode>mode == DImode)"
++{
++ if (TARGET_AVX512VL)
++ return "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}";
++ else
++ return "vpternlog<ternlogsuffix>\t{$0x55, %g1, %g0, %g0<mask_operand3>|%g0<mask_operand3>, %g0, %g1, 0x55}";
++}
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+- (set_attr "mode" "<sseinsnmode>")])
++ (set (attr "mode")
++ (if_then_else (match_test "TARGET_AVX512VL")
++ (const_string "<sseinsnmode>")
++ (const_string "XI")))
++ (set (attr "enabled")
++ (if_then_else (eq_attr "alternative" "1")
++ (symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
++ (const_int 1)))])
+
+ (define_expand "<sse2_avx2>_andnot<mode>3"
+ [(set (match_operand:VI_AVX2 0 "register_operand")
+--- gcc/testsuite/gcc.target/i386/avx512f-pr94343.c.jj 2020-03-26 17:47:40.008654504 +0100
++++ gcc/testsuite/gcc.target/i386/avx512f-pr94343.c 2020-03-26 17:48:37.169811375 +0100
+@@ -0,0 +1,12 @@
++/* PR target/94343 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -mavx512f -mno-avx512vl" } */
++/* { dg-final { scan-assembler-not "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
++
++typedef int __v4si __attribute__((vector_size (16)));
++
++__v4si
++foo (__v4si a)
++{
++ return ~a;
++}
+--- gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c.jj 2020-03-26 17:48:53.232573115 +0100
++++ gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c 2020-03-26 17:49:08.034352968 +0100
+@@ -0,0 +1,12 @@
++/* PR target/94343 */
++/* { dg-do compile } */
++/* { dg-options "-O2 -mavx512vl" } */
++/* { dg-final { scan-assembler "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
++
++typedef int __v4si __attribute__((vector_size (16)));
++
++__v4si
++foo (__v4si a)
++{
++ return ~a;
++}
diff --git a/sources b/sources
index 634dbf6..c20f1e4 100644
--- a/sources
+++ b/sources
@@ -1,3 +1,3 @@
-SHA512 (gcc-10.0.1-20200325.tar.xz) = 5431edeeb9ef900ce49e4fa13869c63d84c244f846be96f1e782249b0a4ac3c6d5ce73117bd3fb1d2d786e82d394ec0a5ea5cc4615f8cc61d7f6aa43db6a8ce9
+SHA512 (gcc-10.0.1-20200328.tar.xz) = 567f7b9c7b3ac41465bac0354d94f58ab92abe8a5cc2462551397d4bee6071a90ae79c65a4e1d84f51dde6b8639574606675204c78ce0d16f3fc47c169a4ef60
SHA512 (newlib-cygwin-50e2a63b04bdd018484605fbb954fd1bd5147fa0.tar.xz) = 9ceea0b883185fe489724d54a7e909bb6ed4785fcadf80162033dc6a133e2657337175601278e4155d1f8fac275ff9c8a02572aea876166c608774c809f832e9
SHA512 (nvptx-tools-5f6f343a302d620b0868edab376c00b15741e39e.tar.xz) = f6d10db94fa1570ae0f94df073fa3c73c8e5ee16d59070b53d94f7db0de8a031bc44d7f3f1852533da04b625ce758e022263855ed43cfc6867e0708d001e53c7
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