[rpms/gcc] rhel-f41-base: 5.1.1-1

[rpms/gcc] rhel-f41-base: 5.1.1-1

[Jakub Jelinek]

A new commit has been pushed.

Repo   : rpms/gcc
Branch : rhel-f41-base
Commit : b5d17a9ac58a2c6354fabd7b7d8bb5bbe2e43be6
Author : Jakub Jelinek <jakub@redhat.com>
Date   : 2015-04-22T18:13:07+02:00
Stats  : +296/-62 in 6 file(s)
URL    : https://src.fedoraproject.org/rpms/gcc/c/b5d17a9ac58a2c6354fabd7b7d8bb5bbe2e43be6?branch=rhel-f41-base

Log:
5.1.1-1

---
diff --git a/.gitignore b/.gitignore
index 2aa5a83..0a668b2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -16,3 +16,4 @@
 /gcc-5.0.0-20150407.tar.bz2
 /gcc-5.0.1-20150413.tar.bz2
 /gcc-5.0.1-20150417.tar.bz2
+/gcc-5.1.1-20150422.tar.bz2

diff --git a/gcc.spec b/gcc.spec
index 259cc0f..69daff6 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -1,9 +1,9 @@
-%global DATE 20150417
-%global SVNREV 222191
-%global gcc_version 5.0.1
+%global DATE 20150422
+%global SVNREV 222331
+%global gcc_version 5.1.1
 # Note, gcc_release must be integer, if you want to add suffixes to
 # %{release}, append them after %{gcc_release} on Release: line.
-%global gcc_release 0.2
+%global gcc_release 1
 %global _unpackaged_files_terminate_build 0
 %global _performance_build 1
 %global multilib_64_archs sparc64 ppc64 ppc64p7 s390x x86_64
@@ -204,7 +204,8 @@ Patch11: gcc5-no-add-needed.patch
 Patch12: gcc5-libgo-p224.patch
 Patch13: gcc5-aarch64-async-unw-tables.patch
 Patch14: gcc5-libsanitize-aarch64-va42.patch
-Patch15: gcc5-pr65787.patch
+Patch15: gcc5-pr65689.patch
+Patch16: gcc5-pr65780.patch
 
 # On ARM EABI systems, we do want -gnueabi to be part of the
 # target triple.
@@ -771,7 +772,8 @@ package or when debugging this package.
 rm -f libgo/go/crypto/elliptic/p224{,_test}.go
 %patch13 -p0 -b .aarch64-async-unw-tables~
 %patch14 -p0 -b .libsanitize-aarch64-va42~
-%patch15 -p0 -b .pr65787~
+%patch15 -p0 -b .pr65689~
+%patch16 -p0 -b .pr65780~
 
 %if 0%{?_enable_debug_packages}
 mkdir dwz-wrapper
@@ -3070,6 +3072,15 @@ fi
 %doc rpm.doc/changelogs/libcc1/ChangeLog*
 
 %changelog
+* Wed Apr 22 2015 Jakub Jelinek <jakub@redhat.com> 5.1.1-1
+- update from the 5 branch
+  - GCC 5.1 release
+  - PRs debug/65807, testsuite/65767
+- improve handling of asm constraints that don't accept REG nor MEM
+  at -O0 (PR target/65689)
+- improve common handling in non-pic code on s390{,x}, aarch64 and
+  arm (PR target/65780)
+
 * Fri Apr 17 2015 Jakub Jelinek <jakub@redhat.com> 5.0.1-0.2
 - update from the 5 branch
   - PRs bootstrap/62077, bootstrap/65763, debug/65771, ipa/65765,

diff --git a/gcc5-pr65689.patch b/gcc5-pr65689.patch
new file mode 100644
index 0000000..0dcdd5e
--- /dev/null
+++ b/gcc5-pr65689.patch
@@ -0,0 +1,231 @@
+2015-04-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/65689
+	* genpreds.c (struct constraint_data): Add maybe_allows_reg and
+	maybe_allows_mem bitfields.
+	(maybe_allows_none_start, maybe_allows_none_end,
+	maybe_allows_reg_start, maybe_allows_reg_end, maybe_allows_mem_start,
+	maybe_allows_mem_end): New variables.
+	(compute_maybe_allows): New function.
+	(add_constraint): Use it to initialize maybe_allows_reg and
+	maybe_allows_mem fields.
+	(choose_enum_order): Sort the non-is_register/is_const_int/is_memory/
+	is_address constraints such that those that allow neither mem nor
+	reg come first, then those that only allow reg but not mem, then
+	those that only allow mem but not reg, then the rest.
+	(write_allows_reg_mem_function): New function.
+	(write_tm_preds_h): Call it.
+	* stmt.c (parse_output_constraint, parse_input_constraint): Use
+	the generated insn_extra_constraint_allows_reg_mem function
+	instead of always setting *allows_reg = true; *allows_mem = true;
+	for unknown extra constraints.
+
+	* gcc.target/aarch64/c-output-template-4.c: New test.
+
+--- gcc/genpreds.c.jj	2015-04-08 18:23:50.643556230 +0200
++++ gcc/genpreds.c	2015-04-17 17:44:23.097650110 +0200
+@@ -640,12 +640,14 @@ struct constraint_data
+   const char *regclass;  /* for register constraints */
+   rtx exp;               /* for other constraints */
+   unsigned int lineno;   /* line of definition */
+-  unsigned int is_register  : 1;
+-  unsigned int is_const_int : 1;
+-  unsigned int is_const_dbl : 1;
+-  unsigned int is_extra     : 1;
+-  unsigned int is_memory    : 1;
+-  unsigned int is_address   : 1;
++  unsigned int is_register	: 1;
++  unsigned int is_const_int	: 1;
++  unsigned int is_const_dbl	: 1;
++  unsigned int is_extra		: 1;
++  unsigned int is_memory	: 1;
++  unsigned int is_address	: 1;
++  unsigned int maybe_allows_reg : 1;
++  unsigned int maybe_allows_mem : 1;
+ };
+ 
+ /* Overview of all constraints beginning with a given letter.  */
+@@ -691,6 +693,9 @@ static unsigned int satisfied_start;
+ static unsigned int const_int_start, const_int_end;
+ static unsigned int memory_start, memory_end;
+ static unsigned int address_start, address_end;
++static unsigned int maybe_allows_none_start, maybe_allows_none_end;
++static unsigned int maybe_allows_reg_start, maybe_allows_reg_end;
++static unsigned int maybe_allows_mem_start, maybe_allows_mem_end;
+ 
+ /* Convert NAME, which contains angle brackets and/or underscores, to
+    a string that can be used as part of a C identifier.  The string
+@@ -711,6 +716,34 @@ mangle (const char *name)
+   return XOBFINISH (rtl_obstack, const char *);
+ }
+ 
++/* Return a bitmask, bit 1 if EXP maybe allows a REG/SUBREG, 2 if EXP
++   maybe allows a MEM.  Bits should be clear only when we are sure it
++   will not allow a REG/SUBREG or a MEM.  */
++static int
++compute_maybe_allows (rtx exp)
++{
++  switch (GET_CODE (exp))
++    {
++    case IF_THEN_ELSE:
++      /* Conservative answer is like IOR, of the THEN and ELSE branches.  */
++      return compute_maybe_allows (XEXP (exp, 1))
++	     | compute_maybe_allows (XEXP (exp, 2));
++    case AND:
++      return compute_maybe_allows (XEXP (exp, 0))
++	     & compute_maybe_allows (XEXP (exp, 1));
++    case IOR:
++      return compute_maybe_allows (XEXP (exp, 0))
++	     | compute_maybe_allows (XEXP (exp, 1));
++    case MATCH_CODE:
++      if (*XSTR (exp, 1) == '\0')
++	return (strstr (XSTR (exp, 0), "reg") != NULL ? 1 : 0)
++	       | (strstr (XSTR (exp, 0), "mem") != NULL ? 2 : 0);
++      /* FALLTHRU */
++    default:
++      return 3;
++    }
++}
++
+ /* Add one constraint, of any sort, to the tables.  NAME is its name;
+    REGCLASS is the register class, if any; EXP is the expression to
+    test, if any;  IS_MEMORY and IS_ADDRESS indicate memory and address
+@@ -866,6 +899,11 @@ add_constraint (const char *name, const
+   c->is_extra = !(regclass || is_const_int || is_const_dbl);
+   c->is_memory = is_memory;
+   c->is_address = is_address;
++  int maybe_allows = 3;
++  if (exp)
++    maybe_allows = compute_maybe_allows (exp);
++  c->maybe_allows_reg = (maybe_allows & 1) != 0;
++  c->maybe_allows_mem = (maybe_allows & 2) != 0;
+ 
+   c->next_this_letter = *slot;
+   *slot = c;
+@@ -940,8 +978,30 @@ choose_enum_order (void)
+       enum_order[next++] = c;
+   address_end = next;
+ 
++  maybe_allows_none_start = next;
++  FOR_ALL_CONSTRAINTS (c)
++    if (!c->is_register && !c->is_const_int && !c->is_memory && !c->is_address
++	&& !c->maybe_allows_reg && !c->maybe_allows_mem)
++      enum_order[next++] = c;
++  maybe_allows_none_end = next;
++
++  maybe_allows_reg_start = next;
++  FOR_ALL_CONSTRAINTS (c)
++    if (!c->is_register && !c->is_const_int && !c->is_memory && !c->is_address
++	&& c->maybe_allows_reg && !c->maybe_allows_mem)
++      enum_order[next++] = c;
++  maybe_allows_reg_end = next;
++
++  maybe_allows_mem_start = next;
++  FOR_ALL_CONSTRAINTS (c)
++    if (!c->is_register && !c->is_const_int && !c->is_memory && !c->is_address
++	&& !c->maybe_allows_reg && c->maybe_allows_mem)
++      enum_order[next++] = c;
++  maybe_allows_mem_end = next;
++
+   FOR_ALL_CONSTRAINTS (c)
+-    if (!c->is_register && !c->is_const_int && !c->is_memory && !c->is_address)
++    if (!c->is_register && !c->is_const_int && !c->is_memory && !c->is_address
++	&& c->maybe_allows_reg && c->maybe_allows_mem)
+       enum_order[next++] = c;
+   gcc_assert (next == num_constraints);
+ }
+@@ -1229,6 +1289,41 @@ write_range_function (const char *name,
+ 	    "}\n\n", name);
+ }
+ 
++/* Write a definition for insn_extra_constraint_allows_reg_mem function.  */
++static void
++write_allows_reg_mem_function (void)
++{
++  printf ("static inline void\n"
++	  "insn_extra_constraint_allows_reg_mem (enum constraint_num c,\n"
++	  "\t\t\t\t      bool *allows_reg, bool *allows_mem)\n"
++	  "{\n");
++  if (maybe_allows_none_start != maybe_allows_none_end)
++    printf ("  if (c >= CONSTRAINT_%s && c <= CONSTRAINT_%s)\n"
++	    "    return;\n",
++	    enum_order[maybe_allows_none_start]->c_name,
++	    enum_order[maybe_allows_none_end - 1]->c_name);
++  if (maybe_allows_reg_start != maybe_allows_reg_end)
++    printf ("  if (c >= CONSTRAINT_%s && c <= CONSTRAINT_%s)\n"
++	    "    {\n"
++	    "      *allows_reg = true;\n"
++	    "      return;\n"
++	    "    }\n",
++	    enum_order[maybe_allows_reg_start]->c_name,
++	    enum_order[maybe_allows_reg_end - 1]->c_name);
++  if (maybe_allows_mem_start != maybe_allows_mem_end)
++    printf ("  if (c >= CONSTRAINT_%s && c <= CONSTRAINT_%s)\n"
++	    "    {\n"
++	    "      *allows_mem = true;\n"
++	    "      return;\n"
++	    "    }\n",
++	    enum_order[maybe_allows_mem_start]->c_name,
++	    enum_order[maybe_allows_mem_end - 1]->c_name);
++  printf ("  (void) c;\n"
++	  "  *allows_reg = true;\n"
++	  "  *allows_mem = true;\n"
++	  "}\n\n");
++}
++
+ /* VEC is a list of key/value pairs, with the keys being lower bounds
+    of a range.  Output a decision tree that handles the keys covered by
+    [VEC[START], VEC[END]), returning FALLBACK for keys lower then VEC[START]'s.
+@@ -1326,6 +1421,7 @@ write_tm_preds_h (void)
+ 			    memory_start, memory_end);
+       write_range_function ("insn_extra_address_constraint",
+ 			    address_start, address_end);
++      write_allows_reg_mem_function ();
+ 
+       if (constraint_max_namelen > 1)
+         {
+--- gcc/stmt.c.jj	2015-04-08 18:23:50.660555956 +0200
++++ gcc/stmt.c	2015-04-17 17:36:50.623044548 +0200
+@@ -342,13 +342,7 @@ parse_output_constraint (const char **co
+ 	else if (insn_extra_memory_constraint (cn))
+ 	  *allows_mem = true;
+ 	else
+-	  {
+-	    /* Otherwise we can't assume anything about the nature of
+-	       the constraint except that it isn't purely registers.
+-	       Treat it like "g" and hope for the best.  */
+-	    *allows_reg = true;
+-	    *allows_mem = true;
+-	  }
++	  insn_extra_constraint_allows_reg_mem (cn, allows_reg, allows_mem);
+ 	break;
+       }
+ 
+@@ -465,13 +459,7 @@ parse_input_constraint (const char **con
+ 	else if (insn_extra_memory_constraint (cn))
+ 	  *allows_mem = true;
+ 	else
+-	  {
+-	    /* Otherwise we can't assume anything about the nature of
+-	       the constraint except that it isn't purely registers.
+-	       Treat it like "g" and hope for the best.  */
+-	    *allows_reg = true;
+-	    *allows_mem = true;
+-	  }
++	  insn_extra_constraint_allows_reg_mem (cn, allows_reg, allows_mem);
+ 	break;
+       }
+ 
+--- gcc/testsuite/gcc.target/aarch64/c-output-template-4.c.jj	2015-04-17 17:48:27.588654584 +0200
++++ gcc/testsuite/gcc.target/aarch64/c-output-template-4.c	2015-04-17 17:48:22.149743468 +0200
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O0" } */
++
++void
++test (void)
++{
++    __asm__ ("@ %c0" : : "S" (&test + 4));
++}
++
++/* { dg-final { scan-assembler "@ test\\+4" } } */

diff --git a/gcc5-pr65780.patch b/gcc5-pr65780.patch
new file mode 100644
index 0000000..9e98fcb
--- /dev/null
+++ b/gcc5-pr65780.patch
@@ -0,0 +1,46 @@
+2015-04-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/65780
+	* config/s390/linux.h (TARGET_BINDS_LOCAL_P): Define to
+	default_binds_local_p_2.
+	* config/arm/linux-elf.h (TARGET_BINDS_LOCAL_P): Likewise.
+	* config/aarch64/aarch64-linux.h (TARGET_BINDS_LOCAL_P): Likewise.
+
+--- gcc/config/s390/linux.h.jj	2015-01-05 13:07:16.000000000 +0100
++++ gcc/config/s390/linux.h	2015-04-22 17:39:38.880273650 +0200
+@@ -90,4 +90,10 @@ along with GCC; see the file COPYING3.
+ #undef TARGET_LIBC_HAS_FUNCTION
+ #define TARGET_LIBC_HAS_FUNCTION gnu_libc_has_function
+ 
++/* Uninitialized common symbols in non-PIE executables, even with
++   strong definitions in dependent shared libraries, will resolve
++   to COPY relocated symbol in the executable.  See PR65780.  */
++#undef TARGET_BINDS_LOCAL_P
++#define TARGET_BINDS_LOCAL_P default_binds_local_p_2
++
+ #endif
+--- gcc/config/arm/linux-elf.h.jj	2015-01-05 13:07:16.000000000 +0100
++++ gcc/config/arm/linux-elf.h	2015-04-22 17:42:35.979420149 +0200
+@@ -118,3 +118,9 @@
+ /* Add .note.GNU-stack.  */
+ #undef NEED_INDICATE_EXEC_STACK
+ #define NEED_INDICATE_EXEC_STACK	1
++
++/* Uninitialized common symbols in non-PIE executables, even with
++   strong definitions in dependent shared libraries, will resolve
++   to COPY relocated symbol in the executable.  See PR65780.  */
++#undef TARGET_BINDS_LOCAL_P
++#define TARGET_BINDS_LOCAL_P default_binds_local_p_2
+--- gcc/config/aarch64/aarch64-linux.h.jj	2015-01-05 13:07:17.000000000 +0100
++++ gcc/config/aarch64/aarch64-linux.h	2015-04-22 17:40:46.395185820 +0200
+@@ -69,4 +69,10 @@
+ 
+ #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+ 
++/* Uninitialized common symbols in non-PIE executables, even with
++   strong definitions in dependent shared libraries, will resolve
++   to COPY relocated symbol in the executable.  See PR65780.  */
++#undef TARGET_BINDS_LOCAL_P
++#define TARGET_BINDS_LOCAL_P default_binds_local_p_2
++
+ #endif  /* GCC_AARCH64_LINUX_H */

diff --git a/gcc5-pr65787.patch b/gcc5-pr65787.patch
deleted file mode 100644
index c5674ed..0000000
--- a/gcc5-pr65787.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-2015-04-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
-
-	PR target/65787
-	* config/rs6000/rs6000.c (rtx_is_swappable_p): Remove previous
-	fix; ensure that a subsequent SH_NONE operand does not overwrite
-	an existing *special value.
-
---- gcc/config/rs6000/rs6000.c.jj	2015-04-17 19:09:59.000000000 +0200
-+++ gcc/config/rs6000/rs6000.c	2015-04-17 19:28:43.264784372 +0200
-@@ -34204,17 +34204,6 @@ rtx_is_swappable_p (rtx op, unsigned int
-       else
- 	return 0;
- 
--    case PARALLEL:
--      /* A vec_extract operation may be wrapped in a PARALLEL with a
--	 clobber, so account for that possibility.  */
--      if (XVECLEN (op, 0) != 2)
--	return 0;
--
--      if (GET_CODE (XVECEXP (op, 0, 1)) != CLOBBER)
--	return 0;
--
--      return rtx_is_swappable_p (XVECEXP (op, 0, 0), special);
--
-     case UNSPEC:
-       {
- 	/* Various operations are unsafe for this optimization, at least
-@@ -34296,10 +34285,11 @@ rtx_is_swappable_p (rtx op, unsigned int
-       {
- 	unsigned int special_op = SH_NONE;
- 	ok &= rtx_is_swappable_p (XEXP (op, i), &special_op);
-+	if (special_op == SH_NONE)
-+	  continue;
- 	/* Ensure we never have two kinds of special handling
- 	   for the same insn.  */
--	if (*special != SH_NONE && special_op != SH_NONE
--	    && *special != special_op)
-+	if (*special != SH_NONE && *special != special_op)
- 	  return 0;
- 	*special = special_op;
-       }
-@@ -34308,10 +34298,11 @@ rtx_is_swappable_p (rtx op, unsigned int
- 	{
- 	  unsigned int special_op = SH_NONE;
- 	  ok &= rtx_is_swappable_p (XVECEXP (op, i, j), &special_op);
-+	  if (special_op == SH_NONE)
-+	    continue;
- 	  /* Ensure we never have two kinds of special handling
- 	     for the same insn.  */
--	  if (*special != SH_NONE && special_op != SH_NONE
--	      && *special != special_op)
-+	  if (*special != SH_NONE && *special != special_op)
- 	    return 0;
- 	  *special = special_op;
- 	}

diff --git a/sources b/sources
index f3ec04d..d9f887f 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-95324ee9bce6045eb2b0c0ffecd91f64  gcc-5.0.1-20150417.tar.bz2
+75d3cea2e9d56d53de2db2a8c8f8bb1d  gcc-5.1.1-20150422.tar.bz2