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* [rpms/gcc] rhel-f41-base: 4.9.1-6
@ 2026-06-29 12:26 Jakub Jelinek
0 siblings, 0 replies; only message in thread
From: Jakub Jelinek @ 2026-06-29 12:26 UTC (permalink / raw)
To: git-commits
A new commit has been pushed.
Repo : rpms/gcc
Branch : rhel-f41-base
Commit : af3b5a8175d468ddbedfa829f3009a55eccf89bd
Author : Jakub Jelinek <jakub@redhat.com>
Date : 2014-08-13T11:30:49+02:00
Stats : +439/-4 in 6 file(s)
URL : https://src.fedoraproject.org/rpms/gcc/c/af3b5a8175d468ddbedfa829f3009a55eccf89bd?branch=rhel-f41-base
Log:
4.9.1-6
---
diff --git a/.gitignore b/.gitignore
index c613c52..287760c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -19,3 +19,4 @@
/gcc-4.9.1-20140717.tar.bz2
/gcc-4.9.1-20140801.tar.bz2
/gcc-4.9.1-20140807.tar.bz2
+/gcc-4.9.1-20140813.tar.bz2
diff --git a/gcc.spec b/gcc.spec
index 9252a1f..686db3d 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -1,9 +1,9 @@
-%global DATE 20140807
-%global SVNREV 213696
+%global DATE 20140813
+%global SVNREV 213898
%global gcc_version 4.9.1
# Note, gcc_release must be integer, if you want to add suffixes to
# %{release}, append them after %{gcc_release} on Release: line.
-%global gcc_release 5
+%global gcc_release 6
%global _unpackaged_files_terminate_build 0
%global _performance_build 1
%global multilib_64_archs sparc64 ppc64 ppc64p7 s390x x86_64
@@ -197,6 +197,9 @@ Patch14: gcc49-pr56493.patch
Patch15: gcc49-color-auto.patch
Patch16: gcc49-libgo-p224.patch
Patch17: gcc49-aarch64-async-unw-tables.patch
+Patch18: gcc49-aarch64-unwind-opt.patch
+Patch19: gcc49-pr62098.patch
+Patch20: gcc49-pr62103.patch
Patch1100: cloog-%{cloog_version}-ppc64le-config.patch
@@ -724,6 +727,9 @@ package or when debugging this package.
%patch16 -p0 -b .libgo-p224~
rm -f libgo/go/crypto/elliptic/p224{,_test}.go
%patch17 -p0 -b .aarch64-async-unw-tables~
+%patch18 -p0 -b .aarch64-unwind-opt~
+%patch19 -p0 -b .pr62098~
+%patch20 -p0 -b .pr62103~
%if 0%{?_enable_debug_packages}
cat > split-debuginfo.sh <<\EOF
@@ -2796,6 +2802,16 @@ fi
%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_version}/plugin
%changelog
+* Wed Aug 13 2014 Jakub Jelinek <jakub@redhat.com> 4.9.1-6
+- update from the 4.9 branch
+ - PRs c++/58714, c++/60872, c++/61959, c++/61994, fortran/61999,
+ libstdc++/61667, other/61962, tree-optimization/60707
+ - fix scheduler deps handling of inc with clobbers vs. mem user (#1126463,
+ PR target/62025)
+- optimize slightly aarch64 unwind info
+- backport arm vcvtf2i fix from trunk (PR target/62098)
+- backport fold_ctor_reference big-endian fix (PR middle-end/62103)
+
* Thu Aug 7 2014 Jakub Jelinek <jakub@redhat.com> 4.9.1-5
- update from the 4.9 branch
- PRs debug/61923, libstdc++/58962, libstdc++/61374, libstdc++/61390,
diff --git a/gcc49-aarch64-unwind-opt.patch b/gcc49-aarch64-unwind-opt.patch
new file mode 100644
index 0000000..3ad55ab
--- /dev/null
+++ b/gcc49-aarch64-unwind-opt.patch
@@ -0,0 +1,338 @@
+2014-08-08 Richard Henderson <rth@redhat.com>
+
+ * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Add
+ cfi_ops argument, for restore put REG_CFA_RESTORE notes into
+ *cfi_ops rather than on individual insns. Cleanup.
+ (aarch64_save_or_restore_callee_save_registers): Likewise.
+ (aarch64_expand_prologue): Adjust caller.
+ (aarch64_expand_epilogue): Likewise. Cleanup. Emit queued cfi_ops
+ on the stack restore insn.
+
+--- gcc/config/aarch64/aarch64.c.jj 2014-07-08 17:38:17.398231989 +0200
++++ gcc/config/aarch64/aarch64.c 2014-08-13 10:02:45.599757706 +0200
+@@ -1810,8 +1810,7 @@ aarch64_register_saved_on_entry (int reg
+
+ static void
+ aarch64_save_or_restore_fprs (int start_offset, int increment,
+- bool restore, rtx base_rtx)
+-
++ bool restore, rtx base_rtx, rtx *cfi_ops)
+ {
+ unsigned regno;
+ unsigned regno2;
+@@ -1819,16 +1818,16 @@ aarch64_save_or_restore_fprs (int start_
+ rtx (*gen_mem_ref)(enum machine_mode, rtx)
+ = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
+
+-
+ for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
+ {
+ if (aarch64_register_saved_on_entry (regno))
+ {
+- rtx mem;
++ rtx mem, reg1;
+ mem = gen_mem_ref (DFmode,
+ plus_constant (Pmode,
+ base_rtx,
+ start_offset));
++ reg1 = gen_rtx_REG (DFmode, regno);
+
+ for (regno2 = regno + 1;
+ regno2 <= V31_REGNUM
+@@ -1840,56 +1839,51 @@ aarch64_save_or_restore_fprs (int start_
+ if (regno2 <= V31_REGNUM &&
+ aarch64_register_saved_on_entry (regno2))
+ {
+- rtx mem2;
++ rtx mem2, reg2;
+ /* Next highest register to be saved. */
+ mem2 = gen_mem_ref (DFmode,
+ plus_constant
+ (Pmode,
+ base_rtx,
+ start_offset + increment));
++ reg2 = gen_rtx_REG (DFmode, regno2);
++
+ if (restore == false)
+ {
+- insn = emit_insn
+- ( gen_store_pairdf (mem, gen_rtx_REG (DFmode, regno),
+- mem2, gen_rtx_REG (DFmode, regno2)));
+-
++ insn = emit_insn (gen_store_pairdf (mem, reg1, mem2, reg2));
++ /* The first part of a frame-related parallel insn
++ is always assumed to be relevant to the frame
++ calculations; subsequent parts, are only
++ frame-related if explicitly marked. */
++ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
++ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ else
+ {
+- insn = emit_insn
+- ( gen_load_pairdf (gen_rtx_REG (DFmode, regno), mem,
+- gen_rtx_REG (DFmode, regno2), mem2));
+-
+- add_reg_note (insn, REG_CFA_RESTORE,
+- gen_rtx_REG (DFmode, regno));
+- add_reg_note (insn, REG_CFA_RESTORE,
+- gen_rtx_REG (DFmode, regno2));
++ emit_insn (gen_load_pairdf (reg1, mem, reg2, mem2));
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops);
+ }
+
+- /* The first part of a frame-related parallel insn
+- is always assumed to be relevant to the frame
+- calculations; subsequent parts, are only
+- frame-related if explicitly marked. */
+- RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
+ regno = regno2;
+ start_offset += increment * 2;
+ }
+ else
+ {
+ if (restore == false)
+- insn = emit_move_insn (mem, gen_rtx_REG (DFmode, regno));
++ {
++ insn = emit_move_insn (mem, reg1);
++ RTX_FRAME_RELATED_P (insn) = 1;
++ }
+ else
+ {
+- insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem);
+- add_reg_note (insn, REG_CFA_RESTORE,
+- gen_rtx_REG (DImode, regno));
++ emit_move_insn (reg1, mem);
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
+ }
+ start_offset += increment;
+ }
+- RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ }
+-
+ }
+
+
+@@ -1897,13 +1891,14 @@ aarch64_save_or_restore_fprs (int start_
+ restore's have to happen. */
+ static void
+ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
+- bool restore)
++ bool restore, rtx *cfi_ops)
+ {
+ rtx insn;
+ rtx base_rtx = stack_pointer_rtx;
+ HOST_WIDE_INT start_offset = offset;
+ HOST_WIDE_INT increment = UNITS_PER_WORD;
+- rtx (*gen_mem_ref)(enum machine_mode, rtx) = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
++ rtx (*gen_mem_ref)(enum machine_mode, rtx)
++ = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
+ unsigned limit = (frame_pointer_needed)? R28_REGNUM: R30_REGNUM;
+ unsigned regno;
+ unsigned regno2;
+@@ -1912,11 +1907,13 @@ aarch64_save_or_restore_callee_save_regi
+ {
+ if (aarch64_register_saved_on_entry (regno))
+ {
+- rtx mem;
++ rtx mem, reg1;
++
+ mem = gen_mem_ref (Pmode,
+ plus_constant (Pmode,
+ base_rtx,
+ start_offset));
++ reg1 = gen_rtx_REG (DImode, regno);
+
+ for (regno2 = regno + 1;
+ regno2 <= limit
+@@ -1928,56 +1925,54 @@ aarch64_save_or_restore_callee_save_regi
+ if (regno2 <= limit &&
+ aarch64_register_saved_on_entry (regno2))
+ {
+- rtx mem2;
++ rtx mem2, reg2;
+ /* Next highest register to be saved. */
+ mem2 = gen_mem_ref (Pmode,
+ plus_constant
+ (Pmode,
+ base_rtx,
+ start_offset + increment));
++ reg2 = gen_rtx_REG (DImode, regno2);
++
+ if (restore == false)
+ {
+- insn = emit_insn
+- ( gen_store_pairdi (mem, gen_rtx_REG (DImode, regno),
+- mem2, gen_rtx_REG (DImode, regno2)));
+-
++ insn = emit_insn (gen_store_pairdi (mem, reg1, mem2, reg2));
++ /* The first part of a frame-related parallel insn
++ is always assumed to be relevant to the frame
++ calculations; subsequent parts, are only
++ frame-related if explicitly marked. */
++ RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
++ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ else
+ {
+- insn = emit_insn
+- ( gen_load_pairdi (gen_rtx_REG (DImode, regno), mem,
+- gen_rtx_REG (DImode, regno2), mem2));
+-
+- add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno));
+- add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
++ emit_insn (gen_load_pairdi (reg1, mem, reg2, mem2));
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops);
+ }
+
+- /* The first part of a frame-related parallel insn
+- is always assumed to be relevant to the frame
+- calculations; subsequent parts, are only
+- frame-related if explicitly marked. */
+- RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
+- 1)) = 1;
+ regno = regno2;
+ start_offset += increment * 2;
+ }
+ else
+ {
+ if (restore == false)
+- insn = emit_move_insn (mem, gen_rtx_REG (DImode, regno));
++ {
++ insn = emit_move_insn (mem, reg1);
++ RTX_FRAME_RELATED_P (insn) = 1;
++ }
+ else
+ {
+- insn = emit_move_insn (gen_rtx_REG (DImode, regno), mem);
+- add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno));
++ emit_move_insn (reg1, mem);
++ *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
+ }
+ start_offset += increment;
+ }
+- RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ }
+
+- aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
+-
++ aarch64_save_or_restore_fprs (start_offset, increment, restore,
++ base_rtx, cfi_ops);
+ }
+
+ /* AArch64 stack frames generated by this compiler look like:
+@@ -2179,7 +2174,7 @@ aarch64_expand_prologue (void)
+ }
+
+ aarch64_save_or_restore_callee_save_registers
+- (fp_offset + cfun->machine->frame.hardfp_offset, 0);
++ (fp_offset + cfun->machine->frame.hardfp_offset, 0, NULL);
+ }
+
+ /* when offset >= 512,
+@@ -2248,15 +2243,18 @@ aarch64_expand_epilogue (bool for_sibcal
+ insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+ hard_frame_pointer_rtx,
+ GEN_INT (- fp_offset)));
++ /* CFA should be calculated from the value of SP from now on. */
++ add_reg_note (insn, REG_CFA_ADJUST_CFA,
++ gen_rtx_SET (VOIDmode, stack_pointer_rtx,
++ plus_constant (Pmode, hard_frame_pointer_rtx,
++ -fp_offset)));
+ RTX_FRAME_RELATED_P (insn) = 1;
+- /* As SP is set to (FP - fp_offset), according to the rules in
+- dwarf2cfi.c:dwarf2out_frame_debug_expr, CFA should be calculated
+- from the value of SP from now on. */
+ cfa_reg = stack_pointer_rtx;
+ }
+
++ rtx cfi_ops = NULL;
+ aarch64_save_or_restore_callee_save_registers
+- (fp_offset + cfun->machine->frame.hardfp_offset, 1);
++ (fp_offset + cfun->machine->frame.hardfp_offset, 1, &cfi_ops);
+
+ /* Restore the frame pointer and lr if the frame pointer is needed. */
+ if (offset > 0)
+@@ -2264,6 +2262,8 @@ aarch64_expand_epilogue (bool for_sibcal
+ if (frame_pointer_needed)
+ {
+ rtx mem_fp, mem_lr;
++ rtx reg_fp = hard_frame_pointer_rtx;
++ rtx reg_lr = gen_rtx_REG (DImode, LR_REGNUM);
+
+ if (fp_offset)
+ {
+@@ -2276,52 +2276,36 @@ aarch64_expand_epilogue (bool for_sibcal
+ stack_pointer_rtx,
+ fp_offset
+ + UNITS_PER_WORD));
+- insn = emit_insn (gen_load_pairdi (hard_frame_pointer_rtx,
+- mem_fp,
+- gen_rtx_REG (DImode,
+- LR_REGNUM),
+- mem_lr));
++ emit_insn (gen_load_pairdi (reg_fp, mem_fp, reg_lr, mem_lr));
++
++ insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
++ GEN_INT (offset)));
+ }
+ else
+ {
+ insn = emit_insn (gen_loadwb_pairdi_di
+- (stack_pointer_rtx,
+- stack_pointer_rtx,
+- hard_frame_pointer_rtx,
+- gen_rtx_REG (DImode, LR_REGNUM),
+- GEN_INT (offset),
++ (stack_pointer_rtx, stack_pointer_rtx,
++ reg_fp, reg_lr, GEN_INT (offset),
+ GEN_INT (GET_MODE_SIZE (DImode) + offset)));
+- RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
+- add_reg_note (insn, REG_CFA_ADJUST_CFA,
+- (gen_rtx_SET (Pmode, stack_pointer_rtx,
+- plus_constant (Pmode, cfa_reg,
+- offset))));
+- }
+-
+- /* The first part of a frame-related parallel insn
+- is always assumed to be relevant to the frame
+- calculations; subsequent parts, are only
+- frame-related if explicitly marked. */
+- RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
+- RTX_FRAME_RELATED_P (insn) = 1;
+- add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
+- add_reg_note (insn, REG_CFA_RESTORE,
+- gen_rtx_REG (DImode, LR_REGNUM));
+-
+- if (fp_offset)
+- {
+- insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+- GEN_INT (offset)));
+- RTX_FRAME_RELATED_P (insn) = 1;
+ }
++ cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg_fp, cfi_ops);
++ cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg_lr, cfi_ops);
+ }
+ else
+ {
+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+ GEN_INT (offset)));
+- RTX_FRAME_RELATED_P (insn) = 1;
+ }
++ cfi_ops = alloc_reg_note (REG_CFA_ADJUST_CFA,
++ gen_rtx_SET (VOIDmode, stack_pointer_rtx,
++ plus_constant (Pmode, cfa_reg,
++ offset)),
++ cfi_ops);
++ REG_NOTES (insn) = cfi_ops;
++ RTX_FRAME_RELATED_P (insn) = 1;
+ }
++ else
++ gcc_assert (cfi_ops == NULL);
+
+ /* Stack adjustment for exception handler. */
+ if (crtl->calls_eh_return)
diff --git a/gcc49-pr62098.patch b/gcc49-pr62098.patch
new file mode 100644
index 0000000..13be97a
--- /dev/null
+++ b/gcc49-pr62098.patch
@@ -0,0 +1,30 @@
+2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ PR target/62098
+ * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint.
+ Remove unnecessary attributes.
+
+--- gcc/config/arm/vfp.md (revision 213860)
++++ gcc/config/arm/vfp.md (revision 213861)
+@@ -1264,17 +1264,15 @@ (define_insn "*combine_vcvt_f64_<FCVTI32
+ )
+
+ (define_insn "*combine_vcvtf2i"
+- [(set (match_operand:SI 0 "s_register_operand" "=r")
+- (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
++ [(set (match_operand:SI 0 "s_register_operand" "=t")
++ (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0")
+ (match_operand 2
+ "const_double_vcvt_power_of_two" "Dp")))))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
+- "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
++ "vcvt%?.s32.f32\\t%0, %1, %v2"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
+- (set_attr "ce_count" "2")
+- (set_attr "type" "f_cvtf2i")
+- (set_attr "length" "8")]
++ (set_attr "type" "f_cvtf2i")]
+ )
+
+ ;; Store multiple insn used in function prologue.
diff --git a/gcc49-pr62103.patch b/gcc49-pr62103.patch
new file mode 100644
index 0000000..b381e78
--- /dev/null
+++ b/gcc49-pr62103.patch
@@ -0,0 +1,50 @@
+2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR middle-end/62103
+ * gimple-fold.c (fold_ctor_reference): Don't fold in presence of
+ bitfields, that is when size doesn't match the size of type or the
+ size of the constructor.
+
+ * gcc.c-torture/execute/bitfld-6.c: New test.
+
+--- gcc/gimple-fold.c (revision 213845)
++++ gcc/gimple-fold.c (revision 213846)
+@@ -4355,8 +4355,10 @@ fold_ctor_reference (tree type, tree cto
+ result. */
+ if (!AGGREGATE_TYPE_P (TREE_TYPE (ctor)) && !offset
+ /* VIEW_CONVERT_EXPR is defined only for matching sizes. */
+- && operand_equal_p (TYPE_SIZE (type),
+- TYPE_SIZE (TREE_TYPE (ctor)), 0))
++ && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
++ && TREE_CODE (TYPE_SIZE (TREE_TYPE (ctor))) == INTEGER_CST
++ && !compare_tree_int (TYPE_SIZE (type), size)
++ && !compare_tree_int (TYPE_SIZE (TREE_TYPE (ctor)), size))
+ {
+ ret = canonicalize_constructor_val (unshare_expr (ctor), from_decl);
+ ret = fold_unary (VIEW_CONVERT_EXPR, type, ret);
+--- gcc/testsuite/gcc.c-torture/execute/bitfld-6.c (revision 0)
++++ gcc/testsuite/gcc.c-torture/execute/bitfld-6.c (revision 213846)
+@@ -0,0 +1,23 @@
++union U
++{
++ const int a;
++ unsigned b : 20;
++};
++
++static union U u = { 0x12345678 };
++
++/* Constant folding used to fail to account for endianness when folding a
++ union. */
++
++int
++main (void)
++{
++#ifdef __BYTE_ORDER__
++#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
++ return u.b - 0x45678;
++#else
++ return u.b - 0x12345;
++#endif
++#endif
++ return 0;
++}
diff --git a/sources b/sources
index b983a45..7eaadd5 100644
--- a/sources
+++ b/sources
@@ -1,3 +1,3 @@
e34fca0540d840e5d0f6427e98c92252 cloog-0.18.1.tar.gz
-d0748685c39ced9837fdb30467524cc9 gcc-4.9.1-20140807.tar.bz2
+aebbdaf7f7e28a92e0ed5b4aec401fd5 gcc-4.9.1-20140813.tar.bz2
e039bfcfb6c2ab039b8ee69bf883e824 isl-0.12.2.tar.bz2
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