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* [rpms/rocblas] epel10: Update to 7.2.0
@ 2026-06-11 14:33 Tom Rix
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From: Tom Rix @ 2026-06-11 14:33 UTC (permalink / raw)
To: git-commits
A new commit has been pushed.
Repo : rpms/rocblas
Branch : epel10
Commit : 3a7f0cfe6d18d6eda25ada8143e9d9f7315b9f84
Author : Tom Rix <Tom.Rix@amd.com>
Date : 2026-02-07T08:19:23-08:00
Stats : +29/-35 in 9 file(s)
URL : https://src.fedoraproject.org/rpms/rocblas/c/3a7f0cfe6d18d6eda25ada8143e9d9f7315b9f84?branch=epel10
Log:
Update to 7.2.0
Signed-off-by: Tom Rix <Tom.Rix@amd.com>
---
diff --git a/.gitignore b/.gitignore
index 985899d..ac175f0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,3 +14,5 @@
/rocBLAS-7.1.0.tar.gz
/rocblas-7.1.1.tar.gz
/Tensile-7.1.1.tar.gz
+/Tensile-7.2.0.tar.gz
+/rocblas-7.2.0.tar.gz
diff --git a/0001-tensile-add-cmake-arches.patch b/0001-tensile-add-cmake-arches.patch
index 79bb3c5..ffe5265 100644
--- a/0001-tensile-add-cmake-arches.patch
+++ b/0001-tensile-add-cmake-arches.patch
@@ -1,4 +1,4 @@
-From 4d9f28f69cbe468a95e06d8ca81746cab785e9da Mon Sep 17 00:00:00 2001
+From 97d064fb6acae49c3543b3eb88c211bde4c82401 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Thu, 30 Oct 2025 07:59:11 -0700
Subject: [PATCH] tensile add cmake arches
@@ -21,5 +21,5 @@ index e8a28d3bfeda..2147db4d5a93 100644
"gfx1201")
--
-2.51.0
+2.52.0
diff --git a/0001-tensile-fedora-gpus.patch b/0001-tensile-fedora-gpus.patch
index db96faf..9d55d0f 100644
--- a/0001-tensile-fedora-gpus.patch
+++ b/0001-tensile-fedora-gpus.patch
@@ -1,4 +1,4 @@
-From 3c17363a401de821280a9d4da6e0fba4490c88ce Mon Sep 17 00:00:00 2001
+From a31c5dca12d81f81f3aaf9629e8c6ea0660fd06d Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Thu, 30 Oct 2025 06:59:47 -0700
Subject: [PATCH] tensile fedora gpus
@@ -212,7 +212,7 @@ index cacc1848b7e0..41330270c618 100644
'v_dot4c_i32_i8': False,
'v_fma_f16': True,
diff --git a/Tensile/Common.py b/Tensile/Common.py
-index 86c6c5778293..d16ca848cbc8 100644
+index 9370c3ef09d4..8b6b43111877 100644
--- a/Tensile/Common.py
+++ b/Tensile/Common.py
@@ -248,9 +248,9 @@ globalParameters["MaxFileName"] = 64 # If a file name would be long
@@ -227,7 +227,7 @@ index 86c6c5778293..d16ca848cbc8 100644
(12,0,0), (12,0,1)] # assembly kernels writer supports these architectures
globalParameters["KeepBuildTmp"] = True # Do not remove build artifacts during the build process or build_tmp after build completes
-@@ -325,7 +325,7 @@ architectureMap = {
+@@ -326,7 +326,7 @@ architectureMap = {
'gfx1010':'navi10', 'gfx1011':'navi12', 'gfx1012':'navi14',
'gfx1030':'navi21', 'gfx1031':'navi22', 'gfx1032':'navi23', 'gfx1034':'navi24', 'gfx1035':'rembrandt',
'gfx1100':'navi31', 'gfx1101':'navi32', 'gfx1102':'navi33', 'gfx1103':'gfx1103',
@@ -236,7 +236,7 @@ index 86c6c5778293..d16ca848cbc8 100644
'gfx1200':'gfx1200',
'gfx1201':'gfx1201'
}
-@@ -2464,7 +2464,7 @@ def assignGlobalParameters( config, capabilitiesCache: Optional[dict] = None ):
+@@ -2466,7 +2466,7 @@ def assignGlobalParameters( config, capabilitiesCache: Optional[dict] = None ):
if os.name == "nt":
globalParameters["CurrentISA"] = (9,0,6)
printWarning("Failed to detect ISA so forcing (gfx906) on windows")
@@ -336,5 +336,5 @@ index a21e584d291a..cb1c085258c9 100644
template <typename MyProblem, typename MySolution = typename MyProblem::Solution>
--
-2.51.0
+2.52.0
diff --git a/0001-tensile-gfx1036.patch b/0001-tensile-gfx1036.patch
index 9b7b08e..b0a7f15 100644
--- a/0001-tensile-gfx1036.patch
+++ b/0001-tensile-gfx1036.patch
@@ -1,4 +1,4 @@
-From 26080c363fb030d822e0317d3d6093789d5b1c4a Mon Sep 17 00:00:00 2001
+From 0bd27b4c7bbd913967583158983a9b6077c956f5 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Fri, 7 Nov 2025 10:07:52 -0800
Subject: [PATCH] tensile gfx1036
@@ -162,7 +162,7 @@ index c4bdc4775300..ea9d7567b58e 100644
'v_dot4c_i32_i8': False,
'v_fma_f16': True,
diff --git a/Tensile/Common.py b/Tensile/Common.py
-index 5ab3f6381fcf..157ac5abd233 100644
+index 140d4dbe58c2..a7d2ab5cd760 100644
--- a/Tensile/Common.py
+++ b/Tensile/Common.py
@@ -248,7 +248,7 @@ globalParameters["MaxFileName"] = 64 # If a file name would be long
@@ -174,7 +174,7 @@ index 5ab3f6381fcf..157ac5abd233 100644
(11,0,0), (11,0,1), (11,0,2), (11,0,3),
(11,5,0), (11,5,1), (11,5,2), (11,5,3),
(12,0,0), (12,0,1)] # assembly kernels writer supports these architectures
-@@ -323,7 +323,7 @@ architectureMap = {
+@@ -324,7 +324,7 @@ architectureMap = {
'gfx942':'aquavanjaram942', 'gfx942:xnack+':'aquavanjaram942', 'gfx942:xnack-':'aquavanjaram942',
'gfx950':'gfx950', 'gfx950:xnack+':'gfx950', 'gfx950:xnack-':'gfx950',
'gfx1010':'navi10', 'gfx1011':'navi12', 'gfx1012':'navi14',
@@ -238,5 +238,5 @@ index 77c9ced2cc35..852c41f60e8d 100644
return "TensileLibrary_*_gfx1100";
case LazyLoadingInit::gfx1101:
--
-2.51.0
+2.52.0
diff --git a/0001-tensile-gfx1153.patch b/0001-tensile-gfx1153.patch
index 8dd92bc..acf9bf6 100644
--- a/0001-tensile-gfx1153.patch
+++ b/0001-tensile-gfx1153.patch
@@ -1,4 +1,4 @@
-From 984dd95e0ab0458266a5375510524072cedbb11b Mon Sep 17 00:00:00 2001
+From 1c66a051e819a40e9bbe6bdd8d54124baf001f00 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Thu, 30 Oct 2025 07:15:18 -0700
Subject: [PATCH] tensile gfx1153
@@ -66,7 +66,7 @@ index 41330270c618..c4bdc4775300 100644
'v_dot4c_i32_i8': False,
'v_fma_f16': True,
diff --git a/Tensile/Common.py b/Tensile/Common.py
-index d16ca848cbc8..ad3e8a26b5db 100644
+index 8b6b43111877..a4a8bb524da0 100644
--- a/Tensile/Common.py
+++ b/Tensile/Common.py
@@ -250,7 +250,7 @@ globalParameters["SupportedISA"] = [(8,0,3),
@@ -78,7 +78,7 @@ index d16ca848cbc8..ad3e8a26b5db 100644
(12,0,0), (12,0,1)] # assembly kernels writer supports these architectures
globalParameters["KeepBuildTmp"] = True # Do not remove build artifacts during the build process or build_tmp after build completes
-@@ -325,7 +325,7 @@ architectureMap = {
+@@ -326,7 +326,7 @@ architectureMap = {
'gfx1010':'navi10', 'gfx1011':'navi12', 'gfx1012':'navi14',
'gfx1030':'navi21', 'gfx1031':'navi22', 'gfx1032':'navi23', 'gfx1034':'navi24', 'gfx1035':'rembrandt',
'gfx1100':'navi31', 'gfx1101':'navi32', 'gfx1102':'navi33', 'gfx1103':'gfx1103',
@@ -87,7 +87,7 @@ index d16ca848cbc8..ad3e8a26b5db 100644
'gfx1200':'gfx1200',
'gfx1201':'gfx1201'
}
-@@ -2464,7 +2464,7 @@ def assignGlobalParameters( config, capabilitiesCache: Optional[dict] = None ):
+@@ -2466,7 +2466,7 @@ def assignGlobalParameters( config, capabilitiesCache: Optional[dict] = None ):
if os.name == "nt":
globalParameters["CurrentISA"] = (9,0,6)
printWarning("Failed to detect ISA so forcing (gfx906) on windows")
@@ -161,5 +161,5 @@ index cb1c085258c9..77c9ced2cc35 100644
return "";
}
--
-2.51.0
+2.52.0
diff --git a/0001-tensile-ignore-cache-check.patch b/0001-tensile-ignore-cache-check.patch
index 55b861b..abe4231 100644
--- a/0001-tensile-ignore-cache-check.patch
+++ b/0001-tensile-ignore-cache-check.patch
@@ -1,4 +1,4 @@
-From f6f1389482fb882c5414f6a74b4f289f1c9c951f Mon Sep 17 00:00:00 2001
+From c0eae8b2bbe0a94fd6961d0802edf8c6f68227d0 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Thu, 30 Oct 2025 07:23:52 -0700
Subject: [PATCH] tensile ignore cache check
@@ -8,10 +8,10 @@ Subject: [PATCH] tensile ignore cache check
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/Tensile/Common.py b/Tensile/Common.py
-index ad3e8a26b5db..5ab3f6381fcf 100644
+index a4a8bb524da0..140d4dbe58c2 100644
--- a/Tensile/Common.py
+++ b/Tensile/Common.py
-@@ -2103,17 +2103,7 @@ def GetAsmCaps(isaVersion: IsaVersion, hipVersion: SemanticVersion, cachedAsmCap
+@@ -2104,17 +2104,7 @@ def GetAsmCaps(isaVersion: IsaVersion, hipVersion: SemanticVersion, cachedAsmCap
derivedAsmCaps["SupportedSource"] = True
@@ -31,5 +31,5 @@ index ad3e8a26b5db..5ab3f6381fcf 100644
# check if derived caps matches asm cap cache
if not ignoreCacheCheck:
--
-2.51.0
+2.52.0
diff --git a/0001-tensile-set-default-paths.patch b/0001-tensile-set-default-paths.patch
index c90c2ea..f00414b 100644
--- a/0001-tensile-set-default-paths.patch
+++ b/0001-tensile-set-default-paths.patch
@@ -1,4 +1,4 @@
-From c08f67b1248ddbf5d0c2b188b85a9374f5f12c20 Mon Sep 17 00:00:00 2001
+From 0a4fb93121619f3fae1fc3ebba4f64a8d053ce93 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Sat, 20 Sep 2025 08:43:09 -0700
Subject: [PATCH] tensile set default paths
@@ -32,5 +32,5 @@ index ee9cbeeea9f3..c328b74bcbc2 100644
searchPaths.extend(
[
--
-2.51.0
+2.52.0
diff --git a/rocblas.spec b/rocblas.spec
index 336a349..c316f63 100644
--- a/rocblas.spec
+++ b/rocblas.spec
@@ -27,8 +27,8 @@
%endif
%global upstreamname rocblas
-%global rocm_release 7.1
-%global rocm_patch 1
+%global rocm_release 7.2
+%global rocm_patch 0
%global rocm_version %{rocm_release}.%{rocm_patch}
%bcond_with compat
@@ -151,15 +151,7 @@
%global gpu_list %{rocm_gpu_list_default}
%global _gpu_list gfx1100
-%if %{with compat}
-%bcond_without bundled_tensile
-%else
-%if 0%{?suse_version}
%bcond_without bundled_tensile
-%else
-%bcond_with bundled_tensile
-%endif
-%endif
Name: rocblas%{pkg_suffix}
Summary: BLAS implementation for ROCm
@@ -172,7 +164,7 @@ Release: 3%{?dist}
Source0: %{url}/archive/%{commit0}/rocm-libraries-%{shortcommit0}.tar.gz
%else
Version: %{rocm_version}
-Release: 7%{?dist}
+Release: 1%{?dist}
Source0: %{url}/releases/download/rocm-%{version}/%{upstreamname}.tar.gz#/%{upstreamname}-%{version}.tar.gz
%endif
diff --git a/sources b/sources
index 22af380..6749db9 100644
--- a/sources
+++ b/sources
@@ -1,2 +1,2 @@
-SHA512 (rocblas-7.1.1.tar.gz) = ea31432ff5350175c1e9d1a7aaaa3e92b6a9925313067e68a22b3ec671906733774e06350d1bc9dafee67d97394b365102d3280e01e80612f9b429850e14db52
-SHA512 (Tensile-7.1.1.tar.gz) = 05ad08c0f80abf9458332a4708f9c4d7ecc694a892d4578faec8c1d88ec78e5aab7bdaf7506802e62b81dd69b0203bb652b14a9e10de2e675dd2aa45ee92448b
+SHA512 (Tensile-7.2.0.tar.gz) = fc1946aa1c3ebddbdab02f6966d7ed08d937e17518d192b31a54d2084972188d8c71b8d1c58f0fd5d8455cc9a3e11414f1f7dbbfd284e0c90538264b9af2c4d0
+SHA512 (rocblas-7.2.0.tar.gz) = 5301a8822c4d3b9ea4223ebe001a80522605d0b2634d11e824043026fe8b148c424c4ffaa4402133dcb28857363c273aa56caa3533b91b0b6147e0289350ca1f
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