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* [rpms/uboot-tools] rawhide: Update brcmstb pcie patch
@ 2026-06-03 11:32 Peter Robinson
0 siblings, 0 replies; only message in thread
From: Peter Robinson @ 2026-06-03 11:32 UTC (permalink / raw)
To: git-commits
A new commit has been pushed.
Repo : rpms/uboot-tools
Branch : rawhide
Commit : 7131d07d8690764d5b941d12c0e16102886fa33e
Author : Peter Robinson <pbrobinson@gmail.com>
Date : 2026-06-03T12:31:56+01:00
Stats : +178/-176 in 1 file(s)
URL : https://src.fedoraproject.org/rpms/uboot-tools/c/7131d07d8690764d5b941d12c0e16102886fa33e?branch=rawhide
Log:
Update brcmstb pcie patch
---
diff --git a/ARM-RPi5-Enable-PCIe.patch b/ARM-RPi5-Enable-PCIe.patch
index f86ae64..db052eb 100644
--- a/ARM-RPi5-Enable-PCIe.patch
+++ b/ARM-RPi5-Enable-PCIe.patch
@@ -1,32 +1,33 @@
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To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -66,8 +67,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
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@@ -128,36 +129,35 @@ index 7a1de22e0ae..7a2faaa4de6 100644
/* SoC bus */
.virt = 0x107c000000UL,
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+Subject: [PATCH v5 2/9] pci: brcmstb: Fix PCIe bus numbers
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -197,8 +197,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
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unsigned int pci_func = PCI_FUNC(bdf);
int idx;
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+Subject: [PATCH v5 3/9] pci: brcmstb: Support different variants using a cfg
struct
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
@@ -318,8 +319,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
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+Message-Id: <20260601103925.6B2FE68C7B@verein.lst.de>
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From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
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@@ -556,12 +557,12 @@ index 47c0802df23..5cb39dfd136 100644
};
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-Subject: [PATCH v4 4/9] reset: Add RPi5 brcmstb reset facilities
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+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
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+Subject: [PATCH v5 4/9] reset: Add RPi5 brcmstb reset facilities
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -625,8 +626,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
=?unknown-8bit?q?=2Ede?=
-Message-Id: <20260523163430.DA8E768D09@verein.lst.de>
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+Message-Id: <20260601103927.7616B68D05@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:27 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -807,36 +808,35 @@ index 00000000000..7861f7c9baf
+ .priv_auto = sizeof(struct brcmstb_reset),
+};
-From patchwork Sat May 23 16:34:33 2026
+From patchwork Mon Jun 1 10:39:29 2026
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-References: <20260523163239.8EEA768BEB@verein.lst.de>
-Subject: [PATCH v4 5/9] reset: Add RPi5 rescal reset facilities
+ id 751D668D09; Mon, 1 Jun 2026 12:39:29 +0200 (CEST)
+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
+References: <20260601103557.022EB68B05@verein.lst.de>
+Subject: [PATCH v5 5/9] reset: Add RPi5 rescal reset facilities
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -876,8 +876,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
=?unknown-8bit?q?=2Ede?=
-Message-Id: <20260523163433.3B46568D0D@verein.lst.de>
-Date: Sat, 23 May 2026 18:34:33 +0200 (CEST)
+Message-Id: <20260601103929.751D668D09@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:29 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -1064,36 +1064,35 @@ index 00000000000..fc8fcfa8b3f
+ .priv_auto = sizeof(struct brcm_rescal_reset),
+};
-From patchwork Sat May 23 16:34:35 2026
+From patchwork Mon Jun 1 10:39:31 2026
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MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Torsten Duwe <duwe@lst.de>
-X-Patchwork-Id: 2243369
+X-Patchwork-Id: 2247318
X-Patchwork-Delegate: pbrobinson@gmail.com
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+ (client-ip=85.214.62.61; helo=phobos.denx.de;
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- [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
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-References: <20260523163239.8EEA768BEB@verein.lst.de>
-Subject: [PATCH v4 6/9] pci: brcmstb: Get and use bridge and rescal reset
+ id BD8CC68D0D; Mon, 1 Jun 2026 12:39:31 +0200 (CEST)
+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
+References: <20260601103557.022EB68B05@verein.lst.de>
+Subject: [PATCH v5 6/9] pci: brcmstb: Get and use bridge and rescal reset
properties
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
@@ -1134,8 +1133,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
=?unknown-8bit?q?=2Ede?=
-Message-Id: <20260523163435.E58D768D12@verein.lst.de>
-Date: Sat, 23 May 2026 18:34:35 +0200 (CEST)
+Message-Id: <20260601103931.BD8CC68D0D@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:31 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -1163,11 +1162,11 @@ Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Tested-by: Pedro Falcato <pfalcato@suse.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
- drivers/pci/pcie_brcmstb.c | 70 +++++++++++++++++++++++++++++++++++---
- 1 file changed, 65 insertions(+), 5 deletions(-)
+ drivers/pci/pcie_brcmstb.c | 71 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 66 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-index 5cb39dfd136..4d253440de9 100644
+index 5cb39dfd136..012b501078a 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -21,6 +21,7 @@
@@ -1187,7 +1186,7 @@ index 5cb39dfd136..4d253440de9 100644
const struct brcm_pcie_cfg_data *pcie_cfg;
};
-@@ -143,14 +146,57 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val)
+@@ -143,14 +146,58 @@ static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val)
writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
}
@@ -1204,9 +1203,9 @@ index 5cb39dfd136..4d253440de9 100644
+ }
+
+ ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset);
-+ if (ret) {
++ if (ret)
+ printf("Unable to get bridge reset\n");
-+ }
++
+ return ret;
+}
+
@@ -1225,7 +1224,7 @@ index 5cb39dfd136..4d253440de9 100644
+{
+ int ret = 0;
+
-+ if (pcie->bridge_reset.dev)
++ if (reset_valid(&pcie->bridge_reset))
+ {
+ if (val)
+ ret = reset_assert(&pcie->bridge_reset);
@@ -1236,17 +1235,18 @@ index 5cb39dfd136..4d253440de9 100644
+ val ? "" : "de", ret);
+ return ret;
+ }
++
if (val)
setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
RGR1_SW_INIT_1_INIT_MASK);
else
clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
RGR1_SW_INIT_1_INIT_MASK);
-+ return ret;
++ return 0;
}
/**
-@@ -405,16 +451,25 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -405,16 +452,25 @@ static int brcm_pcie_probe(struct udevice *dev)
int num_out_wins = 0;
u64 rc_bar2_offset, rc_bar2_size;
unsigned int scb_size_val;
@@ -1274,7 +1274,7 @@ index 5cb39dfd136..4d253440de9 100644
if (pcie->pcie_cfg->type != BCM2712)
pcie->pcie_cfg->perst_set(pcie, 1);
/*
-@@ -424,8 +479,9 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -424,8 +480,9 @@ static int brcm_pcie_probe(struct udevice *dev)
udelay(100);
/* Take the bridge out of reset */
@@ -1286,7 +1286,7 @@ index 5cb39dfd136..4d253440de9 100644
clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG],
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
-@@ -607,6 +663,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev)
+@@ -607,6 +664,10 @@ static int brcm_pcie_of_to_plat(struct udevice *dev)
pcie->gen = max_link_speed;
pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev);
@@ -1298,12 +1298,12 @@ index 5cb39dfd136..4d253440de9 100644
}
-From patchwork Sat May 23 16:34:38 2026
+From patchwork Mon Jun 1 10:39:34 2026
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MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Torsten Duwe <duwe@lst.de>
-X-Patchwork-Id: 2243370
+X-Patchwork-Id: 2247319
X-Patchwork-Delegate: pbrobinson@gmail.com
Return-Path: <u-boot-bounces@lists.denx.de>
X-Original-To: incoming@patchwork.ozlabs.org
@@ -1317,17 +1317,17 @@ Received: from phobos.denx.de (phobos.denx.de
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
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+ by legolas.ozlabs.org (Postfix) with ESMTPS id 4gTVpv2npJz1yDY
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- for <u-boot@lists.denx.de>; Sat, 23 May 2026 18:34:39 +0200 (CEST)
+ by phobos.denx.de (Postfix) with ESMTPS id BFE818489E
+ for <u-boot@lists.denx.de>; Mon, 1 Jun 2026 12:39:35 +0200 (CEST)
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- id 6EF7568C4E; Sat, 23 May 2026 18:34:38 +0200 (CEST)
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-References: <20260523163239.8EEA768BEB@verein.lst.de>
-Subject: [PATCH v4 7/9] pci: brcmstb: Fix iBAR size calculation
+ id 5B8CC68D0E; Mon, 1 Jun 2026 12:39:34 +0200 (CEST)
+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
+References: <20260601103557.022EB68B05@verein.lst.de>
+Subject: [PATCH v5 7/9] pci: brcmstb: Fix iBAR size calculation
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -1367,8 +1367,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
=?unknown-8bit?q?=2Ede?=
-Message-Id: <20260523163438.6EF7568C4E@verein.lst.de>
-Date: Sat, 23 May 2026 18:34:38 +0200 (CEST)
+Message-Id: <20260601103934.5B8CC68D0E@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:34 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -1392,13 +1392,13 @@ Fix inbound window size calculation, like Linux commit 25a98c7270156.
Signed-off-by: Torsten Duwe <duwe@suse.de>
Tested-by: Pedro Falcato <pfalcato@suse.de>
-Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/pci/pcie_brcmstb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-index 4d253440de9..1022f275dc8 100644
+index 012b501078a..164d8e2b7fe 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -101,8 +101,8 @@ static int brcm_pcie_encode_ibar_size(u64 size)
@@ -1413,35 +1413,36 @@ index 4d253440de9..1022f275dc8 100644
/* Something is awry so disable */
-From patchwork Sat May 23 16:34:40 2026
+From patchwork Mon Jun 1 10:39:36 2026
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MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Torsten Duwe <duwe@lst.de>
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+X-Patchwork-Id: 2247320
X-Patchwork-Delegate: pbrobinson@gmail.com
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- id A928768CFE; Sat, 23 May 2026 18:34:40 +0200 (CEST)
-In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de>
-References: <20260523163239.8EEA768BEB@verein.lst.de>
-Subject: [PATCH v4 8/9] pci: brcmstb: rework iBAR handling
+ id A1A3068BFE; Mon, 1 Jun 2026 12:39:36 +0200 (CEST)
+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
+References: <20260601103557.022EB68B05@verein.lst.de>
+Subject: [PATCH v5 8/9] pci: brcmstb: rework iBAR handling
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -1481,8 +1482,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
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-Message-Id: <20260523163440.A928768CFE@verein.lst.de>
-Date: Sat, 23 May 2026 18:34:40 +0200 (CEST)
+Message-Id: <20260601103936.A1A3068BFE@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:36 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -1512,13 +1513,13 @@ in one go, so the code is not 1:1 comparable.
Signed-off-by: Torsten Duwe <duwe@suse.de>
Tested-by: Pedro Falcato <pfalcato@suse.de>
-Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++-----
1 file changed, 131 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-index 1022f275dc8..74d6f2564c2 100644
+index 164d8e2b7fe..624376fe235 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -50,6 +50,29 @@
@@ -1551,7 +1552,7 @@ index 1022f275dc8..74d6f2564c2 100644
enum {
RGR1_SW_INIT_1,
PCIE_HARD_DEBUG,
-@@ -440,17 +463,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
+@@ -441,17 +464,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
}
@@ -1660,7 +1661,7 @@ index 1022f275dc8..74d6f2564c2 100644
int i, ret = 0;
u16 nlw, cls, lnksta;
u32 tmp;
-@@ -495,23 +606,22 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -496,23 +607,22 @@ static int brcm_pcie_probe(struct udevice *dev)
MISC_CTRL_CFG_READ_UR_MODE_MASK |
MISC_CTRL_MAX_BURST_SIZE_128);
@@ -1699,7 +1700,7 @@ index 1022f275dc8..74d6f2564c2 100644
writel(tmp, base + PCIE_MISC_MISC_CTRL);
/* Disable the PCIe->GISB memory window (RC_BAR1) */
-@@ -528,6 +638,8 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -529,6 +639,8 @@ static int brcm_pcie_probe(struct udevice *dev)
/* Clear any interrupts we find on boot */
writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
@@ -1709,35 +1710,36 @@ index 1022f275dc8..74d6f2564c2 100644
brcm_pcie_set_gen(pcie, pcie->gen);
-From patchwork Sat May 23 16:34:43 2026
+From patchwork Mon Jun 1 10:39:40 2026
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X-Patchwork-Submitter: Torsten Duwe <duwe@lst.de>
-X-Patchwork-Id: 2243372
+X-Patchwork-Id: 2247321
X-Patchwork-Delegate: pbrobinson@gmail.com
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-In-Reply-To: <20260523163239.8EEA768BEB@verein.lst.de>
-References: <20260523163239.8EEA768BEB@verein.lst.de>
-Subject: [PATCH v4 9/9] pci: brcmstb: Adapt to AXI bridge
+ id 3EFB268C7B; Mon, 1 Jun 2026 12:39:40 +0200 (CEST)
+In-Reply-To: <20260601103557.022EB68B05@verein.lst.de>
+References: <20260601103557.022EB68B05@verein.lst.de>
+Subject: [PATCH v5 9/9] pci: brcmstb: Adapt to AXI bridge
To: Peter Robinson <pbrobinson@gmail.com>,
Matthias Brugger <mbrugger@suse.com>
Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
@@ -1777,8 +1779,8 @@ Cc: =?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=
=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=
=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=
=?unknown-8bit?q?=2Ede?=
-Message-Id: <20260523163443.8B3CA68D0A@verein.lst.de>
-Date: Sat, 23 May 2026 18:34:43 +0200 (CEST)
+Message-Id: <20260601103940.3EFB268C7B@verein.lst.de>
+Date: Mon, 1 Jun 2026 12:39:40 +0200 (CEST)
From: duwe@lst.de (Torsten Duwe)
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.39
@@ -1806,7 +1808,7 @@ branch. All reworked for the simpler setup code in U-Boot.
Signed-off-by: Torsten Duwe <duwe@suse.de>
Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Tested-by: Pedro Falcato <pfalcato@suse.de>
-Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
.../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 +
drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++-
@@ -1825,10 +1827,10 @@ index 5171c593c72..c72b47e1b10 100644
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-index 74d6f2564c2..a14efa31734 100644
+index 624376fe235..1b03b0a7b05 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
-@@ -554,6 +554,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev)
+@@ -555,6 +555,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev)
}
}
@@ -1859,7 +1861,7 @@ index 74d6f2564c2..a14efa31734 100644
static int brcm_pcie_probe(struct udevice *dev)
{
struct udevice *ctlr = pci_get_controller(dev);
-@@ -599,12 +623,27 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -600,12 +624,27 @@ static int brcm_pcie_probe(struct udevice *dev)
/* Wait for SerDes to be stable */
udelay(100);
@@ -1888,7 +1890,7 @@ index 74d6f2564c2..a14efa31734 100644
tmp = readl(base + PCIE_MISC_MISC_CTRL);
if (pcie->pcie_cfg->type == BCM2712) {
-@@ -624,6 +663,29 @@ static int brcm_pcie_probe(struct udevice *dev)
+@@ -625,6 +664,29 @@ static int brcm_pcie_probe(struct udevice *dev)
}
writel(tmp, base + PCIE_MISC_MISC_CTRL);
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2026-06-03 11:32 [rpms/uboot-tools] rawhide: Update brcmstb pcie patch Peter Robinson
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