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From: Jakub Jelinek <jakub@redhat.com>
To: git-commits@fedoraproject.org
Subject: [rpms/gcc] rhel-f41-base: 14.2.1-3
Date: Mon, 29 Jun 2026 12:30:42 GMT	[thread overview]
Message-ID: <178273624209.1.4277589197664629748.rpms-gcc-dc203d1b7766@fedoraproject.org> (raw)

A new commit has been pushed.

Repo   : rpms/gcc
Branch : rhel-f41-base
Commit : dc203d1b77666d6375f6e5e73dfa9d49a33392a3
Author : Jakub Jelinek <jakub@redhat.com>
Date   : 2024-09-12T20:49:36+02:00
Stats  : +114/-4 in 4 file(s)
URL    : https://src.fedoraproject.org/rpms/gcc/c/dc203d1b77666d6375f6e5e73dfa9d49a33392a3?branch=rhel-f41-base

Log:
14.2.1-3

---
diff --git a/.gitignore b/.gitignore
index a1be907..e67d87e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -24,3 +24,4 @@
 /gcc-14.1.1-20240701.tar.xz
 /gcc-14.2.1-20240801.tar.xz
 /gcc-14.2.1-20240905.tar.xz
+/gcc-14.2.1-20240912.tar.xz

diff --git a/gcc.spec b/gcc.spec
index 55465e5..8b0d09d 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -1,10 +1,10 @@
-%global DATE 20240905
-%global gitrev b30927153ae4cc052bfa564cc3d302eaddaa2c1b
+%global DATE 20240912
+%global gitrev c7a1c1a4bf73b3cb4943c428085fe5cbb433cde4
 %global gcc_version 14.2.1
 %global gcc_major 14
 # Note, gcc_release must be integer, if you want to add suffixes to
 # %%{release}, append them after %%{gcc_release} on Release: line.
-%global gcc_release 2
+%global gcc_release 3
 %global nvptx_tools_gitrev 87ce9dc5999e5fca2e1d3478a30888d9864c9804
 %global newlib_cygwin_gitrev d45261f62a15f8abd94a1031020b9a9f455e4eed
 %global _unpackaged_files_terminate_build 0
@@ -305,6 +305,7 @@ Patch9: gcc14-Wno-format-security.patch
 Patch10: gcc14-rh1574936.patch
 Patch11: gcc14-d-shared-libphobos.patch
 Patch12: gcc14-pr101523.patch
+Patch13: gcc14-pr116621.patch
 
 Patch50: isl-rh2155127.patch
 
@@ -906,6 +907,7 @@ so that there cannot be any synchronization problems.
 %endif
 %patch -P11 -p0 -b .d-shared-libphobos~
 %patch -P12 -p1 -b .pr101523~
+%patch -P13 -p0 -b .pr116621~
 
 %patch -P50 -p0 -b .rh2155127~
 touch -r isl-0.24/m4/ax_prog_cxx_for_build.m4 isl-0.24/m4/ax_prog_cc_for_build.m4
@@ -3616,6 +3618,13 @@ end
 %endif
 
 %changelog
+* Thu Sep 12 2024 Jakub Jelinek <jakub@redhat.com> 14.2.1-3
+- update from releases/gcc-14 branch
+  - PRs c++/116276, c++/116320, c++/116449, c++/116567, c++/116606,
+	c++/116636, ipa/116410, libstdc++/116159, libstdc++/116641,
+	lto/116614, target/116617
+- backport x86_64 va_arg fix (PR target/116621)
+
 * Thu Sep  5 2024 Jakub Jelinek <jakub@redhat.com> 14.2.1-2
 - update from releases/gcc-14 branch
   - PRs c++/88313, c++/112288, c++/115296, c++/115656, c++/116071, c++/116219,

diff --git a/gcc14-pr116621.patch b/gcc14-pr116621.patch
new file mode 100644
index 0000000..caa9e63
--- /dev/null
+++ b/gcc14-pr116621.patch
@@ -0,0 +1,100 @@
+Author: H.J. Lu <hjl.tools@gmail.com>
+Date:   Fri Sep 6 05:24:07 2024 -0700
+
+x86-64: Don't use temp for argument in a TImode register
+
+Don't use temp for a PARALLEL BLKmode argument of an EXPR_LIST expression
+in a TImode register.  Otherwise, the TImode variable will be put in
+the GPR save area which guarantees only 8-byte alignment.
+    
+	PR target/116621
+	* config/i386/i386.cc (ix86_gimplify_va_arg): Don't use temp for
+	a PARALLEL BLKmode container of an EXPR_LIST expression in a
+	TImode register.
+
+	* gcc.target/i386/pr116621.c: New test.
+
+Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
+
+--- gcc/config/i386/i386.cc
++++ gcc/config/i386/i386.cc
+@@ -4908,13 +4908,31 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
+ 
+       examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
+ 
+-      need_temp = (!REG_P (container)
++      bool container_in_reg = false;
++      if (REG_P (container))
++	container_in_reg = true;
++      else if (GET_CODE (container) == PARALLEL
++	       && GET_MODE (container) == BLKmode
++	       && XVECLEN (container, 0) == 1)
++	{
++	  /* Check if it is a PARALLEL BLKmode container of an EXPR_LIST
++	     expression in a TImode register.  In this case, temp isn't
++	     needed.  Otherwise, the TImode variable will be put in the
++	     GPR save area which guarantees only 8-byte alignment.   */
++	  rtx x = XVECEXP (container, 0, 0);
++	  if (GET_CODE (x) == EXPR_LIST
++	      && REG_P (XEXP (x, 0))
++	      && XEXP (x, 1) == const0_rtx)
++	    container_in_reg = true;
++	}
++
++      need_temp = (!container_in_reg
+ 		   && ((needed_intregs && TYPE_ALIGN (type) > 64)
+ 		       || TYPE_ALIGN (type) > 128));
+ 
+       /* In case we are passing structure, verify that it is consecutive block
+          on the register save area.  If not we need to do moves.  */
+-      if (!need_temp && !REG_P (container))
++      if (!need_temp && !container_in_reg)
+ 	{
+ 	  /* Verify that all registers are strictly consecutive  */
+ 	  if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
+--- gcc/testsuite/gcc.target/i386/pr116621.c
++++ gcc/testsuite/gcc.target/i386/pr116621.c
+@@ -0,0 +1,43 @@
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++
++#include <stdarg.h>
++#include <string.h>
++
++union S8302
++{
++  union
++  {
++    double b;
++    int c;
++  } a;
++  long double d;
++  unsigned short int f[5];
++};
++
++union S8302 s8302;
++extern void check8302va (int i, ...);
++
++int
++main (void)
++{
++  memset (&s8302, '\0', sizeof (s8302));
++  s8302.a.b = -221438.250000;
++  check8302va (1, s8302);
++  return 0;
++}
++
++__attribute__((noinline, noclone))
++void
++check8302va (int z, ...)
++{
++  union S8302 arg, *p;
++  va_list ap;
++
++  __builtin_va_start (ap, z);
++  p = &s8302;
++  arg = __builtin_va_arg (ap, union S8302);
++  if (p->a.b != arg.a.b)
++    __builtin_abort ();
++  __builtin_va_end (ap);
++}

diff --git a/sources b/sources
index ee9c0c0..0010d99 100644
--- a/sources
+++ b/sources
@@ -1,4 +1,4 @@
-SHA512 (gcc-14.2.1-20240905.tar.xz) = a1cb68b386633e86c65dedef88a10890f3d2fffb35ecc775bfe87caa0bd6a135858578311e3d8d4a9b09e65c0b90757e01aa081953866fcaf13242a96b697920
+SHA512 (gcc-14.2.1-20240912.tar.xz) = 9a36fd5c2211f348bf18e887861c9123745bfa40837a5f92b1cd0ee0820edb7ef59094caac06870f00ef0d0305f674a5c23cc5aec940132cf581cd18c0368bb2
 SHA512 (isl-0.24.tar.bz2) = aab3bddbda96b801d0f56d2869f943157aad52a6f6e6a61745edd740234c635c38231af20bc3f1a08d416a5e973a90e18249078ed8e4ae2f1d5de57658738e95
 SHA512 (newlib-cygwin-d45261f62a15f8abd94a1031020b9a9f455e4eed.tar.xz) = 31bfc19429797236e268e22b752c5abeabb9c0f39b1058634af8dab329b4f028fc72a35888193c9575f6cee5cf2c069669d79fcb4d4e3a4318f57413452f707d
 SHA512 (nvptx-tools-87ce9dc5999e5fca2e1d3478a30888d9864c9804.tar.xz) = 941e763af8601b89f0e4ec48a2d68ae0a8e70ee1e6ba6859394b021ad7bd7d143cc529f3c35c08d7f84e5554980ddcc97cf05b6c4755c2bc36c91161b79e8cea

                 reply	other threads:[~2026-06-29 12:30 UTC|newest]

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