[rpms/gcc] rhel-f41-base: 10.0.1-0.12

[Jakub Jelinek <jakub@redhat.com>]

A new commit has been pushed.

Repo   : rpms/gcc
Branch : rhel-f41-base
Commit : 9d851d2a4e5e87dd91e0bd48339ba1afb4b5aa2a
Author : Jakub Jelinek <jakub@redhat.com>
Date   : 2020-04-20T16:27:49+02:00
Stats  : +50/-156 in 5 file(s)
URL    : https://src.fedoraproject.org/rpms/gcc/c/9d851d2a4e5e87dd91e0bd48339ba1afb4b5aa2a?branch=rhel-f41-base

Log:
10.0.1-0.12

---
diff --git a/.gitignore b/.gitignore
index a320272..8d6a745 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,3 +9,4 @@
 /gcc-10.0.1-20200311.tar.xz
 /gcc-10.0.1-20200325.tar.xz
 /gcc-10.0.1-20200328.tar.xz
+/gcc-10.0.1-20200420.tar.xz

diff --git a/gcc.spec b/gcc.spec
index 131b321..74cb899 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -1,10 +1,10 @@
-%global DATE 20200328
-%global gitrev 97ad35f30b0d8ed5376febf09cefa2b93f9dc423
+%global DATE 20200420
+%global gitrev dbc1bb99e280740e5bda658a911d9dd3f431ad4d
 %global gcc_version 10.0.1
 %global gcc_major 10
 # Note, gcc_release must be integer, if you want to add suffixes to
 # %%{release}, append them after %%{gcc_release} on Release: line.
-%global gcc_release 0.11
+%global gcc_release 0.12
 %global nvptx_tools_gitrev 5f6f343a302d620b0868edab376c00b15741e39e
 %global newlib_cygwin_gitrev 50e2a63b04bdd018484605fbb954fd1bd5147fa0
 %global _unpackaged_files_terminate_build 0
@@ -265,8 +265,6 @@ Patch8: gcc10-foffload-default.patch
 Patch9: gcc10-Wno-format-security.patch
 Patch10: gcc10-rh1574936.patch
 Patch11: gcc10-d-shared-libphobos.patch
-Patch12: gcc10-pr93069.patch
-Patch13: gcc10-pr94343.patch
 
 # On ARM EABI systems, we do want -gnueabi to be part of the
 # target triple.
@@ -778,8 +776,6 @@ to NVidia PTX capable devices if available.
 %patch10 -p0 -b .rh1574936~
 %endif
 %patch11 -p0 -b .d-shared-libphobos~
-%patch12 -p0 -b .pr93069~
-%patch13 -p0 -b .pr94343~
 
 echo 'Red Hat %{version}-%{gcc_release}' > gcc/DEV-PHASE
 
@@ -3008,6 +3004,51 @@ end
 %endif
 
 %changelog
+* Mon Apr 20 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.12
+- update from trunk
+  - PRs analyzer/94378, bootstrap/89494, bootstrap/92008, c++/67825,
+	c++/79937, c++/85278, c++/86327, c++/88754, c++/90711, c++/90996,
+	c++/91377, c++/91966, c++/92010, c++/92187, c++/92878, c++/93207,
+	c++/93211, c++/93790, c++/94034, c++/94149, c++/94155, c++/94205,
+	c++/94219, c++/94252, c++/94306, c++/94314, c++/94325, c++/94359,
+	c++/94385, c++/94426, c++/94453, c++/94454, c++/94462, c++/94470,
+	c++/94475, c++/94477, c++/94478, c++/94480, c++/94481, c++/94483,
+	c++/94507, c++/94512, c++/94521, c++/94523, c++/94528, c++/94571,
+	c++/94588, c++/94608, c++/94632, c/92326, c/94392, c/94593, d/90136,
+	d/94304, d/94305, d/94315, d/94321, d/94424, d/94425, d/94609,
+	debug/94439, debug/94441, debug/94450, debug/94459, debug/94495,
+	driver/94381, fortran/57129, fortran/85982, fortran/87644,
+	fortran/87923, fortran/91800, fortran/93364, fortran/93498,
+	fortran/93500, fortran/93522, fortran/93686, fortran/93871,
+	fortran/94030, fortran/94090, fortran/94091, fortran/94192,
+	fortran/94246, fortran/94347, fortran/94348, fortran/94386,
+	gcov-profile/93401, gcov-profile/94570, go/94607, ipa/92676,
+	ipa/93621, ipa/93940, ipa/94363, ipa/94434, ipa/94445, ipa/94582,
+	libgcc/94513, libgomp/92843, libstdc++/93960, libstdc++/94498,
+	libstdc++/94520, libstdc++/94562, libstdc++/94565, lto/94612,
+	middle-end/89433, middle-end/93465, middle-end/94412,
+	middle-end/94423, middle-end/94436, middle-end/94465,
+	middle-end/94479, middle-end/94526, middle-end/94539,
+	middle-end/94614, middle-end/94635, objc/94637, other/94629,
+	rtl-optimization/84169, rtl-optimization/87716,
+	rtl-optimization/93946, rtl-optimization/93974,
+	rtl-optimization/94123, rtl-optimization/94291,
+	rtl-optimization/94344, rtl-optimization/94468,
+	rtl-optimization/94516, rtl-optimization/94605,
+	rtl-optimization/94618, target/93053, target/94317, target/94368,
+	target/94396, target/94417, target/94420, target/94435, target/94438,
+	target/94460, target/94467, target/94488, target/94494, target/94500,
+	target/94509, target/94530, target/94542, target/94551, target/94556,
+	target/94561, target/94567, target/94584, target/94603, target/94606,
+	testsuite/93369, testsuite/94079, testsuite/94402, testsuite/94533,
+	tree-optimization/89713, tree-optimization/91322,
+	tree-optimization/93674, tree-optimization/94043,
+	tree-optimization/94398, tree-optimization/94401,
+	tree-optimization/94403, tree-optimization/94443,
+	tree-optimization/94482, tree-optimization/94524,
+	tree-optimization/94573, tree-optimization/94574,
+	tree-optimization/94598, tree-optimization/94621
+
 * Sat Mar 28 2020 Jakub Jelinek <jakub@redhat.com> 10.0.1-0.11
 - update from trunk
   - PRs c++/81349, c++/84733, c++/93810, c++/93824, c++/94057, c++/94078,

diff --git a/gcc10-pr93069.patch b/gcc10-pr93069.patch
deleted file mode 100644
index 3451fb6..0000000
--- a/gcc10-pr93069.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-2020-03-26  Jakub Jelinek  <jakub@redhat.com>
-
-	PR target/93069
-	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
-	<store_mask_constraint> instead of m in output operand constraint.
-	(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
-	%{%3%}.
-
-	* gcc.target/i386/avx512vl-pr93069.c: New test.
-	* gcc.dg/vect/pr93069.c: New test.
-
---- gcc/config/i386/sse.md.jj	2019-12-27 18:16:48.146431083 +0100
-+++ gcc/config/i386/sse.md	2019-12-28 14:43:29.181456611 +0100
-@@ -8782,7 +8782,8 @@
- })
- 
- (define_insn "vec_extract_lo_<mode><mask_name>"
--  [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
-+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
-+					  "=v,v,<store_mask_constraint>")
- 	(vec_select:<ssehalfvecmode>
- 	  (match_operand:V16FI 1 "<store_mask_predicate>"
- 				 "v,<store_mask_constraint>,v")
-@@ -8834,7 +8835,8 @@
- })
- 
- (define_insn "vec_extract_lo_<mode><mask_name>"
--  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
-+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
-+					  "=v,v,<store_mask_constraint>")
- 	(vec_select:<ssehalfvecmode>
- 	  (match_operand:VI8F_256 1 "<store_mask_predicate>"
- 				    "v,<store_mask_constraint>,v")
-@@ -8844,7 +8846,7 @@
-    && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
- {
-   if (<mask_applied>)
--    return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
-+    return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
-   else
-     return "#";
- }
---- gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c.jj	2019-12-28 16:31:30.118695074 +0100
-+++ gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c	2019-12-28 16:32:16.920990539 +0100
-@@ -0,0 +1,12 @@
-+/* PR target/93069 */
-+/* { dg-do assemble { target vect_simd_clones } } */
-+/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
-+/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
-+/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
-+
-+#pragma omp declare simd
-+int
-+foo (int x, int y)
-+{
-+  return x == 0 ? x : y;
-+}
---- gcc/testsuite/gcc.dg/vect/pr93069.c.jj	2019-12-28 16:31:01.822121036 +0100
-+++ gcc/testsuite/gcc.dg/vect/pr93069.c	2019-12-28 16:30:35.503517205 +0100
-@@ -0,0 +1,10 @@
-+/* PR target/93069 */
-+/* { dg-do assemble { target vect_simd_clones } } */
-+/* { dg-options "-O2 -fopenmp-simd" } */
-+
-+#pragma omp declare simd
-+int
-+foo (int x, int y)
-+{
-+  return x == 0 ? x : y;
-+}

diff --git a/gcc10-pr94343.patch b/gcc10-pr94343.patch
deleted file mode 100644
index c8515df..0000000
--- a/gcc10-pr94343.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-2020-03-26  Jakub Jelinek  <jakub@redhat.com>
-
-	PR target/94343
-	* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
-	!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
-	operand is a register.  Don't enable masked variants for V*[QH]Imode.
-
-	* gcc.target/i386/avx512f-pr94343.c: New test.
-	* gcc.target/i386/avx512vl-pr94343.c: New test.
-
---- gcc/config/i386/sse.md.jj	2020-03-06 11:35:46.284074858 +0100
-+++ gcc/config/i386/sse.md	2020-03-26 18:49:39.644131577 +0100
-@@ -12796,14 +12796,29 @@ (define_expand "one_cmpl<mode>2"
- })
- 
- (define_insn "<mask_codefor>one_cmpl<mode>2<mask_name>"
--  [(set (match_operand:VI 0 "register_operand" "=v")
--	(xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm")
--		(match_operand:VI 2 "vector_all_ones_operand" "BC")))]
--  "TARGET_AVX512F"
--  "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}"
-+  [(set (match_operand:VI 0 "register_operand" "=v,v")
-+	(xor:VI (match_operand:VI 1 "nonimmediate_operand" "v,m")
-+		(match_operand:VI 2 "vector_all_ones_operand" "BC,BC")))]
-+  "TARGET_AVX512F
-+   && (!<mask_applied>
-+       || <ssescalarmode>mode == SImode
-+       || <ssescalarmode>mode == DImode)"
-+{
-+  if (TARGET_AVX512VL)
-+    return "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}";
-+  else
-+    return "vpternlog<ternlogsuffix>\t{$0x55, %g1, %g0, %g0<mask_operand3>|%g0<mask_operand3>, %g0, %g1, 0x55}";
-+}
-   [(set_attr "type" "sselog")
-    (set_attr "prefix" "evex")
--   (set_attr "mode" "<sseinsnmode>")])
-+   (set (attr "mode")
-+        (if_then_else (match_test "TARGET_AVX512VL")
-+		      (const_string "<sseinsnmode>")
-+		      (const_string "XI")))
-+   (set (attr "enabled")
-+	(if_then_else (eq_attr "alternative" "1")
-+		      (symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
-+		      (const_int 1)))])
- 
- (define_expand "<sse2_avx2>_andnot<mode>3"
-   [(set (match_operand:VI_AVX2 0 "register_operand")
---- gcc/testsuite/gcc.target/i386/avx512f-pr94343.c.jj	2020-03-26 17:47:40.008654504 +0100
-+++ gcc/testsuite/gcc.target/i386/avx512f-pr94343.c	2020-03-26 17:48:37.169811375 +0100
-@@ -0,0 +1,12 @@
-+/* PR target/94343 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mavx512f -mno-avx512vl" } */
-+/* { dg-final { scan-assembler-not "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
-+
-+typedef int __v4si __attribute__((vector_size (16)));
-+
-+__v4si
-+foo (__v4si a)
-+{
-+  return ~a;
-+}
---- gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c.jj	2020-03-26 17:48:53.232573115 +0100
-+++ gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c	2020-03-26 17:49:08.034352968 +0100
-@@ -0,0 +1,12 @@
-+/* PR target/94343 */
-+/* { dg-do compile } */
-+/* { dg-options "-O2 -mavx512vl" } */
-+/* { dg-final { scan-assembler "vpternlogd\[^\n\r]*xmm\[0-9]*" } } */
-+
-+typedef int __v4si __attribute__((vector_size (16)));
-+
-+__v4si
-+foo (__v4si a)
-+{
-+  return ~a;
-+}

diff --git a/sources b/sources
index c20f1e4..2ebda5a 100644
--- a/sources
+++ b/sources
@@ -1,3 +1,3 @@
-SHA512 (gcc-10.0.1-20200328.tar.xz) = 567f7b9c7b3ac41465bac0354d94f58ab92abe8a5cc2462551397d4bee6071a90ae79c65a4e1d84f51dde6b8639574606675204c78ce0d16f3fc47c169a4ef60
+SHA512 (gcc-10.0.1-20200420.tar.xz) = 3504ebfe7b9fbe59daaf5568ffe3d2c286180dda52ca57600dca370aca51231464e553758148487d1ea15c1d50f1cb72229910592a5137e4901ef537394437e4
 SHA512 (newlib-cygwin-50e2a63b04bdd018484605fbb954fd1bd5147fa0.tar.xz) = 9ceea0b883185fe489724d54a7e909bb6ed4785fcadf80162033dc6a133e2657337175601278e4155d1f8fac275ff9c8a02572aea876166c608774c809f832e9
 SHA512 (nvptx-tools-5f6f343a302d620b0868edab376c00b15741e39e.tar.xz) = f6d10db94fa1570ae0f94df073fa3c73c8e5ee16d59070b53d94f7db0de8a031bc44d7f3f1852533da04b625ce758e022263855ed43cfc6867e0708d001e53c7