[rpms/gcc] rhel-f41-base: 5.0.1-0.2

[Jakub Jelinek <jakub@redhat.com>]

A new commit has been pushed.

Repo   : rpms/gcc
Branch : rhel-f41-base
Commit : f3095e13326261d35b72b8f3b49cbeea14e509fd
Author : Jakub Jelinek <jakub@redhat.com>
Date   : 2015-04-17T19:31:34+02:00
Stats  : +57/-0 in 2 file(s)
URL    : https://src.fedoraproject.org/rpms/gcc/c/f3095e13326261d35b72b8f3b49cbeea14e509fd?branch=rhel-f41-base

Log:
5.0.1-0.2

---
diff --git a/gcc.spec b/gcc.spec
index a4843dd..259cc0f 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -204,6 +204,7 @@ Patch11: gcc5-no-add-needed.patch
 Patch12: gcc5-libgo-p224.patch
 Patch13: gcc5-aarch64-async-unw-tables.patch
 Patch14: gcc5-libsanitize-aarch64-va42.patch
+Patch15: gcc5-pr65787.patch
 
 # On ARM EABI systems, we do want -gnueabi to be part of the
 # target triple.
@@ -770,6 +771,7 @@ package or when debugging this package.
 rm -f libgo/go/crypto/elliptic/p224{,_test}.go
 %patch13 -p0 -b .aarch64-async-unw-tables~
 %patch14 -p0 -b .libsanitize-aarch64-va42~
+%patch15 -p0 -b .pr65787~
 
 %if 0%{?_enable_debug_packages}
 mkdir dwz-wrapper

diff --git a/gcc5-pr65787.patch b/gcc5-pr65787.patch
new file mode 100644
index 0000000..c5674ed
--- /dev/null
+++ b/gcc5-pr65787.patch
@@ -0,0 +1,55 @@
+2015-04-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	PR target/65787
+	* config/rs6000/rs6000.c (rtx_is_swappable_p): Remove previous
+	fix; ensure that a subsequent SH_NONE operand does not overwrite
+	an existing *special value.
+
+--- gcc/config/rs6000/rs6000.c.jj	2015-04-17 19:09:59.000000000 +0200
++++ gcc/config/rs6000/rs6000.c	2015-04-17 19:28:43.264784372 +0200
+@@ -34204,17 +34204,6 @@ rtx_is_swappable_p (rtx op, unsigned int
+       else
+ 	return 0;
+ 
+-    case PARALLEL:
+-      /* A vec_extract operation may be wrapped in a PARALLEL with a
+-	 clobber, so account for that possibility.  */
+-      if (XVECLEN (op, 0) != 2)
+-	return 0;
+-
+-      if (GET_CODE (XVECEXP (op, 0, 1)) != CLOBBER)
+-	return 0;
+-
+-      return rtx_is_swappable_p (XVECEXP (op, 0, 0), special);
+-
+     case UNSPEC:
+       {
+ 	/* Various operations are unsafe for this optimization, at least
+@@ -34296,10 +34285,11 @@ rtx_is_swappable_p (rtx op, unsigned int
+       {
+ 	unsigned int special_op = SH_NONE;
+ 	ok &= rtx_is_swappable_p (XEXP (op, i), &special_op);
++	if (special_op == SH_NONE)
++	  continue;
+ 	/* Ensure we never have two kinds of special handling
+ 	   for the same insn.  */
+-	if (*special != SH_NONE && special_op != SH_NONE
+-	    && *special != special_op)
++	if (*special != SH_NONE && *special != special_op)
+ 	  return 0;
+ 	*special = special_op;
+       }
+@@ -34308,10 +34298,11 @@ rtx_is_swappable_p (rtx op, unsigned int
+ 	{
+ 	  unsigned int special_op = SH_NONE;
+ 	  ok &= rtx_is_swappable_p (XVECEXP (op, i, j), &special_op);
++	  if (special_op == SH_NONE)
++	    continue;
+ 	  /* Ensure we never have two kinds of special handling
+ 	     for the same insn.  */
+-	  if (*special != SH_NONE && special_op != SH_NONE
+-	      && *special != special_op)
++	  if (*special != SH_NONE && *special != special_op)
+ 	    return 0;
+ 	  *special = special_op;
+ 	}